XC3S1600E-4FG320C Xilinx Inc, XC3S1600E-4FG320C Datasheet - Page 198
![no-image](/images/no-image-200.jpg)
XC3S1600E-4FG320C
Manufacturer Part Number
XC3S1600E-4FG320C
Description
FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 320-Pin FBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-4FG320C
Package
320FBGA
Family Name
Spartan®-3E
Device Logic Cells
33192
Device Logic Units
3688
Device System Gates
1600000
Number Of Registers
29504
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
250
Ram Bits
663552
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1600E-4FG320C
Manufacturer:
XILINX
Quantity:
142
Part Number:
XC3S1600E-4FG320C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Pinout Descriptions
Table 143: FT256 Package Pinout (Continued)
198
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
N.C. ( )
N.C. ( )
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IP
IP
IO
IP
IP
IP
IP
IP
IP/VREF_3
IO/VREF_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XC3S250E Pin Name
IO_L17N_3
IO_L17P_3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IP
IP
IO
IP
IP
IP
IP
IP
IP/VREF_3
IO/VREF_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XC3S500E Pin Name
www.xilinx.com
IO_L17N_3
IO_L17P_3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IP
IP
IP
IP
IP
IP
IP
IP
IP/VREF_3
IP/VREF_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XC3S1200E Pin Name
DS312-4 (v3.8) August 26, 2009
FT256
G10
Ball
A16
F11
M4
M3
G1
G6
M2
G7
G8
G9
P1
P2
R1
R2
D2
H1
K4
N3
N2
E2
K6
A1
B9
H2
H7
H8
H9
L4
F2
F5
J6
F6
Product Specification
250E: VREF(I/O)
500E: VREF(I/O)
1200E: INPUT
VREF(INPUT)
250E: N.C.
250E: N.C.
1200E: I/O
1200E: I/O
500E: I/O
500E: I/O
250E: I/O
500E: I/O
1200E:
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VREF
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
R
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