MAX520ACWE Maxim Integrated Products, MAX520ACWE Datasheet - Page 13

• Manufacturer Part Number: MAX520ACWE
• Description: IC DAC QUAD SER 8BIT R/R 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX520ACWE

• Settling Time: 2µs
• Number Of Bits: 8
• Data Interface: I²C, Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 762mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Setting the RST bit high clears all DAC input latches.
The DAC outputs remain unchanged until a STOP con-
dition is detected (Figure 10a). If a reset is issued, the
following output byte is ignored. Subsequent pairs of
command/output bytes overwrite the input latches
(Figure 10b).
All changes made during a transmission affect the
MAX520/MAX521’s outputs only when the transmission
ends and a STOP has been recognized. The R0, R1,
and R2 bits are reserved bits that must be set to zero.
The MAX520/MAX521 are fully compatible with existing
I
SDA has an open drain which pulls the data line low
during the 9th clock pulse. Figure 11 shows a typical
I
It is possible to interrupt a transmission to a MAX520/
MAX521 with a new START (repeated start) condition
(perhaps addressing another device), which leaves the
input latches with data that has not been transferred to
the output latches (Figure 12). Only the currently
addressed device will recognize a STOP condition and
transfer data to its output latches. If the device is left
with data in its input latches, the data can be trans-
ferred to the output latches the next time the device is
addressed, as long as it receives at least one com-
mand byte and a STOP condition.
Figure 10. Resetting DAC Outputs
2
2
(a)
(b)
C systems. SCL and SDA are high-impedance inputs;
C application.
SDA
CONDITION
CONDITION
SDA
START
START
NOTE: X = DON'T CARE
0
0
1
1
ADDRESS BYTE
ADDRESS BYTE
0
0
______________________________________________________________________________________
1
1
AD1 AD0 0 0
AD1 AD0 0 0 0
0 OR AD2
0 OR AD2
Additional START Conditions
Quad/Octal, 2-Wire Serial 8-Bit DACs
ACK
ACK
I
0 0 0 1 0
2
C Compatibility
0
COMMAND BYTE
COMMAND BYTE
0
(RST)
(RST)
1
(
ALL INPUT LATCHES
SET TO 0
0
X X X
X X X
(
ALL INPUT LATCHES
SET TO 0
ACK
ACK
0
0
)
(
STOP
CONDITION
X X X X X X X X
with Rail-to-Rail Outputs
ALL OUTPUTS
SET TO 0
)
Figure 11. Typical I
OUTPUT BYTE
"DUMMY"
)
+5V
ACK
0
OUTPUT BYTE PAIRS
2
SDA SCL
COMMAND BYTE/
C Application Circuit
ADDITIONAL
C
SCL
SDA
SCL
SDA
AD0
AD1
AD2
SCL
SDA
AD0
AD1
(
ALL DAC OUTPUTS SET TO 0 UNLESS
CHANGED BY ADDITIONAL COMMAND
BYTE/OUTPUT BYTE PAIRS
E
MAX521
X24C04
STOP
CONDITION
MAX520
2
XICOR
OCTAL
QUAD
DAC
PROM
DAC
13
)