M4A5-128/64-12VI Lattice, M4A5-128/64-12VI Datasheet - Page 10

• Manufacturer Part Number: M4A5-128/64-12VI
• Description: CPLD ispMACH™ 4A Family 5K Gates 128 Macro Cells 66.7MHz/95MHz EECMOS Technology 5V 100-Pin TQFP Tray
• Manufacturer: Lattice

Specifications of M4A5-128/64-12VI

• Package: 100TQFP
• Family Name: ispMACH™ 4A
• Device System Gates: 5000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 12 ns
• Number Of User I/os: 64
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.7|95 MHz
• Number Of Product Terms Per Macro: 20
• Operating Temperature: -40 to 85 °C

Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization
control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode
chosen only affects clocking and initialization in the macrocell.
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will
generally be used, since it provides more product terms in the allocator.
10
From Logic Allocator
From PAL-Block
Clock Generator
Individual Clock
Product Terms
Product Term
Product Term
Initialization
Initialization
From Logic
PAL-Clock
Individual macrocell resources
PAL-Block
Generator
Common PAL-block resource
Individual
Allocator
From
Power-Up
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Block CLK0
Block CLK1
Power-Up
Reset
Reset
ispMACH 4A Family
a. Synchronous mode
b. Asynchronous mode
Figure 5. Macrocell
SWAP
SWAP
D/T/L
D/T/L
AP
AP
AR
AR
Q
Q
To Output and Input
Switch Matrices
To Output and Input
Switch Matrices
17466G-009
17466G-010