XC5VLX20T-1FF323C Xilinx Inc, XC5VLX20T-1FF323C Datasheet - Page 80

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XC5VLX20T-1FF323C

Manufacturer Part Number
XC5VLX20T-1FF323C
Description
FPGA Virtex®-5 Family 65nm (CMOS) Technology 1V 323-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC5VLX20T-1FF323C

Package
323FCBGA
Family Name
Virtex®-5
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
172
Ram Bits
958464

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Table 96: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode (Cont’d)
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
T
T
PSDCMPLL
PHDCMPLL
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0
driving PLL, PLL CLKOUT0 driving BUFG.
IFF = Input Flip-Flop or Latch.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Symbol
/
No Delay Global Clock and IFF
DCM and PLL in System-Synchronous Mode
Description
(2)
with
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
Device
–0.36
–0.44
–0.59
–0.51
1.97
1.92
2.40
2.46
N/A
N/A
N/A
-3
Speed Grade
–0.41
–0.40
–0.36
–0.44
–0.59
–0.51
–0.31
2.00
2.25
2.08
2.03
2.51
2.64
2.44
-2
–0.41
–0.40
–0.36
–0.44
–0.58
–0.51
–0.30
2.22
2.51
2.21
2.16
2.66
2.89
2.59
-1
Units
ns
ns
ns
ns
ns
ns
ns
80

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