XC3S1200E-4FG320C Xilinx Inc, XC3S1200E-4FG320C Datasheet - Page 171
![no-image](/images/no-image-200.jpg)
XC3S1200E-4FG320C
Manufacturer Part Number
XC3S1200E-4FG320C
Description
FPGA Spartan®-3E Family 1.2M Gates 19512 Cells 572MHz 90nm (CMOS) Technology 1.2V 320-Pin FBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1200E-4FG320C
Package
320FBGA
Family Name
Spartan®-3E
Device Logic Cells
19512
Device Logic Units
2168
Device System Gates
1200000
Number Of Registers
17344
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
250
Ram Bits
516096
Available stocks
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Company:
Part Number:
XC3S1200E-4FG320C
Manufacturer:
XILINX
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4
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User I/Os by Bank
Table 132
distributed between the four I/O banks on the VQ100 pack-
age.
Table 132: User I/Os Per Bank for XC3S100E, XC3S250E, and XC3S500E in the VQ100 Package
Footprint Migration Differences
The production XC3S100E, XC3S250E, and XC3S500E
FPGAs have identical footprints in the VQ100 package.
Designs can migrate between the devices without further
consideration.
DS312-4 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
Top
Right
Bottom
Left
TOTAL
Package
Edge
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
indicates how the 66 available user-I/O pins are
R
I/O Bank
0
1
2
3
Maximum
I/O
15
15
19
17
66
I/O
16
5
6
0
5
www.xilinx.com
INPUT
0
0
0
1
1
All Possible I/O Pins by Type
DUAL
18
21
1
0
2
VREF
1
1
1
1
4
(1)
Pinout Descriptions
CLK
0
24
8
8
8
(2)
(1)
171
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