M28W640HCT70N6E NUMONYX, M28W640HCT70N6E Datasheet - Page 14

• Manufacturer Part Number: M28W640HCT70N6E
• Description: TSOP-1 48 12X20 CUSTD FLASH
• Manufacturer: NUMONYX

Bus operations
3
3.1
3.2
3.3
3.4
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Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby, Automatic Standby and Reset. See
for a summary.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus operations.
Read
Read bus operations are used to output the contents of the memory array, the Electronic
Signature, the Status Register and the common Flash interface. Both Chip Enable and
Output Enable must be at V
should be used to enable the device. Output Enable should be used to gate data onto the
output. The data read depends on the previous command written to the memory (see
Section 4: Command
characteristics, for details of when the output becomes valid.
Read operations of the memory array can be performed in asynchronous page mode, which
provides a fast access time. Data is internally read and stored in a page buffer. The page
has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the
electronic signature, the Status Register, the command Flash interface, the Block Protection
status, the Configuration Register status and the security code are performed as
asynchronous read cycles (Random Read). Both Chip Enable, E, and Output Enable, G,
must be at V
waveforms).
Read mode is the default state of the device when exiting reset or after power-up.
Write
Bus write operations write commands to the memory or latch input data to be programmed.
A write operation is initiated when Chip Enable and Write Enable are at V
Enable at V
Enable or Chip Enable, whichever occurs first.
See
characteristics, for details of the timing requirements.
Output Disable
The data outputs are high impedance when the Output Enable is at V
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable is at V
read mode. The power consumption is reduced to the standby level and the outputs are set
Figure 9
IH
IL
. Commands, input data and addresses are latched on the rising edge of Write
and
in order to read the output of the memory (see
Figure
interface). See
11, Write AC waveforms, and
IL
in order to perform a read operation. The Chip Enable input
Figure 8: Read AC
Table 17
waveforms, and
M28W640HCT, M28W640HCB
Figure 9: Page Read AC
and
IH
Table 2: Bus
Table
and the device is in
IH
.
Table 16: Read AC
IL
18, Write AC
with Output
operations,