72T36125L4-4BB Integrated Device Technology (Idt), 72T36125L4-4BB Datasheet - Page 47

• Manufacturer Part Number: 72T36125L4-4BB
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 256K x 36 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T36125L4-4BB

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 9 Mb
• Organization: 256Kx36
• Data Bus Width: 36 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS = LOW.
WCLK
RCLK
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
WCLK
RCLK
WEN
REN
PAF
WEN
rising edge of WCLK and the rising edge of RCLK is less than t
In IDT Standard mode: D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665 and 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768
for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
In FWFT mode: D = 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
rising edge of RCLK and the rising edge of WCLK is less than t
REN
SKEW2
SKEW2
PAE
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
CLKL
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
ENS
t
ENS
n words in FIFO
n + 1 words in FIFO
t
CLKL
D - (m +1) words in FIFO
t
CLKL
t
ENH
(2)
t
SKEW2
,
1
(3)
t
ENH
(4)
t
PAES
(2)
1
2
SKEW2
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
, then the PAE deassertion may be delayed one extra RCLK cycle.
2
47
t
PAFS
t
ENS
t
ENS
n + 1 words in FIFO
n + 2 words in FIFO
t
ENH
t
SKEW2
(3)
t
(2)
ENH
D - m words in FIFO
,
(3)
1
1
COMMERCIAL AND INDUSTRIAL
(2)
t
PAES
TEMPERATURE RANGES
PAES
2
PAFS
2
t
FEBRUARY 4, 2009
). If the time between the
PAFS
). If the time between the
n words in FIFO
n + 1 words in FIFO
D-(m+1) words
in FIFO
5907 drw29
5907 drw28
(2)
(2)
,
(3)