24AA04-I/SNG Microchip Technology, 24AA04-I/SNG Datasheet - Page 19

• Manufacturer Part Number: 24AA04-I/SNG
• Description: EEPROM Serial-I2C 4K-Bit 2Block x 256 x 8 1.8V/2.5V/3.3V/5V 8-Pin SOIC N Tube
• Manufacturer: Microchip Technology

Specifications of 24AA04-I/SNG

• Package: 8SOIC N
• Interface Type: Serial-I2C
• Density: 4 Kb
• Maximum Operating Frequency: 0.4 MHz
• Maximum Random Access Time: 900 ns
• Typical Operating Supply Voltage: 1.8|2.5|3.3|5 V
• Organization: 2Blockx256x8
• Data Retention: 200(Min) Year
• Operating Temperature: -40 to 85 °C

8.0
Read operations are initiated in much the same way as
write operations with the exception that the R/W bit of
the control byte is set to ‘
of read operations: current address read, random read
and sequential read.
8.1
The 24XX contains an address counter that maintains
the address of the last byte accessed, internally incre-
mented by ‘
operation was to address ‘
the next current address read operation would access
data from address
Upon receipt of the control byte with R/W bit set to ‘
the 24XX issues an acknowledge and transmits the
8-bit data byte. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX discontinues transmission (Figure 8-1).
FIGURE 8-1:
FIGURE 8-2:
FIGURE 8-3:
© 2007 Microchip Technology Inc.
Bus Activity
Master
SDA Line
Bus Activity
Bus Activity
Master
SDA Line
Bus Activity
Bus Activity
Master
SDA Line
Bus Activity
READ OPERATION
Current Address Read
1
’. Therefore, if the previous read or write
S
S
T
A
R
T
n + 1
S
S
T
A
R
T
Control
S
S
T
A
R
T
Byte
CURRENT ADDRESS
READ
RANDOM READ: 128-BIT TO 16 KBIT DEVICES
RANDOM READ: 32 TO 1024 KBIT DEVICES
1
.
’. There are three basic types
Control
n
Byte
Control
’ (
Byte
n
A
C
K
is any legal address),
A
C
K
A
C
K
Data
Byte
Address Byte
High Order
Address
Byte (n)
N
O
A
C
K
24AAXX/24LCXX/24FCXX
1
S
T
O
P
P
’,
A
C
K
A
C
K
S
T
A
R
T
S
Address Byte
Low Order
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the byte address must first
be set. This is done by sending the byte address to the
24XX as part of a write operation (R/W bit set to ‘
Once the byte address is sent, the master generates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address counter is set. The master then issues the
control byte again, but with the R/W bit set to a ‘
24XX will then issue an acknowledge and transmit the
8-bit data byte. The master will not acknowledge the
transfer but does generate a Stop condition, which
causes
(Figure 8-2 and Figure 8-3). After a random Read
command, the internal address counter will increment
to the next address location.
Control
Byte
Random Read
A
C
K
the
S
S
T
A
R
T
A
C
K
24XX
Control
Byte
Data
Byte
to
discontinue
A
C
K
O
N
A
C
K
S
T
O
P
P
DS21930C-page 19
Data
Byte
transmission
N
O
A
C
K
1
’. The
P
S
T
O
P
0’
).