MAX503CAG+T Maxim Integrated Products, MAX503CAG+T Datasheet - Page 15

• Manufacturer Part Number: MAX503CAG+T
• Description: IC DAC 10BIT 5V LP 24-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX503CAG+T

• Settling Time: 25µs
• Number Of Bits: 10
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 640mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

As with any amplifier, the MAX503’s output op amp off-
set can be positive or negative. When the offset is posi-
tive, it is easily accounted for. However, when the offset
is negative, the output cannot follow linearly when there
is no negative supply. In that case, the amplifier output
(VOUT) remains at ground until the DAC voltage is suffi-
cient to overcome the offset and the output becomes
positive. The resulting transfer function is shown in
Figure 13.
Normally, linearity is measured after allowing for zero
error and gain error. Since, in single-supply operation,
the actual value of a negative offset is unknown, it can-
not be accounted for during test. In the MAX503, linear-
ity and gain error are measured from code 3 to code
1023 (see Note 2 under Electrical Characteristics ). The
output amplifier offset does not affect monotonicity, and
these DACs are guaranteed monotonic starting with
code zero. In dual-supply operation, linearity and gain
error are measured from code 0 to 1023.
Best system performance is obtained with printed cir-
cuit boards that use separate analog and digital ground
planes. Wire-wrap boards are not recommended. The
two ground planes should be connected together at the
low-impedance power-supply source.
AGND and REFGND should be connected together,
and then to DGND at the chip. For single-supply appli-
cations, connect V
Figure 11. Bipolar Configuration (-2.048V to +2.048V Output)
__________Applications Information
33µF
REFIN
REFOUT
AGND
DGND
REFGND
______________________________________________________________________________________
SS
to AGND at the chip. The best
and Ground Management
Power-Supply Bypassing
MAX503
Single-Supply Linearity
-5V
+5V
ROFS
VOUT
RFB
5V, Low-Power, Parallel-Input,
V
OUT
Voltage-Output, 10-Bit DAC
ground connection may be achieved by connecting
the AGND, REFGND, and DGND pins together and
connecting that point to the system analog ground
plane. If DGND is connected to the system digital
ground, digital noise may get through to the DAC’s ana-
log portion.
Bypass V
0.1µF ceramic capacitor connected between V
AGND (and between V
capacitors with short leads close to the device.
High-speed data at any of the digital input pins may
couple through the DAC package and cause internal
stray capacitance to appear as noise at the DAC out-
put, even though LDAC and CS are held high (see
Typical Operating Characteristics ). This digital
feedthrough is tested by holding LDAC and CS high
and toggling the data inputs from all 1s to all 0s.
Because of internal stray capacitance, higher-frequen-
cy analog input signals at REFIN may couple to the
output, even when the input digital code is all 0s, as
shown in the Typical Operating Characteristics graph
Analog Feedthrough vs. Frequency. It is tested by set-
ting CLR to low (which sets the DAC latches to all 0s)
and sweeping REFIN.
Figure 12. Four-Quadrant Multiplying Circuit
DD
(and V
REFGND
AGND
DGND
SS
MAX503
in dual-supply mode) with a
V
-5V
SS
+5V
V
SS
DD
and AGND). Mount the
AC Considerations
REFIN
VOUT
Analog Feedthrough
ROFS
Digital Feedthrough
RFB
REFIN
V
OUT
DD
and
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