MAX5821LEUA+T Maxim Integrated Products, MAX5821LEUA+T Datasheet - Page 9

• Manufacturer Part Number: MAX5821LEUA+T
• Description: IC DAC 10BIT DL 2WIRE SER 8-UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX5821LEUA+T

• Settling Time: 4µs
• Number Of Bits: 10
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -

Figure 2. START and STOP Conditions
Figure 3. Early STOP conditions
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5821 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5821 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7-
bit slave address (Figure 4). When idle, the MAX5821
SDA
SCL
SDA
SDA
SCL
SCL
S
_______________________________________________________________________________________
LEGAL STOP CONDITION
ILLEGAL EARLY STOP CONDITION
START
STOP
Dual, 10-Bit, Low-Power, 2-Wire, Serial
S
ILLEGAL
START
r
STOP
Acknowledge Bit (ACK)
Slave Address
P
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit-by-bit, allowing the interface to power down
immediately if an incorrect address is detected. The
LSB of the address word is the
R/W indicates whether the master is writing to or read-
ing from the MAX5821 (R/W = 0 selects the write condi-
tion, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5821 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5821 has four different factory/user-pro-
grammed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to V
MAX5821s to share the same bus.
In write mode (R/W = 0), data that follows the address
byte controls the MAX5821 (Figure 5). Bits C3–C0 con-
figure the MAX5821 (Table 3). Bits D9–D0 are DAC
data. Bits S0 and S1 are sub-bits and are always 0.
Input and DAC registers update on the falling edge of
SCL during the acknowledge bit. Should the write cycle
be prematurely aborted, data is not updated and the
write cycle must be repeated. Figure 6 shows two
example-write data sequences.
The MAX5821 features an extended command mode
that is accessed by setting C3–C0 = 1 and D9–D6 = 0.
Table 2. MAX5821 I
Figure 4. Slave Address Byte Definition
Figure 5. Command Byte Definition
DD
MAX5821M
MAX5821M
MAX5821L
MAX5821L
Voltage-Output DAC
PART
S
sets A0 = 1. This feature allows up to four
C3
A6
C2
A5
C1
A4
V
GND
GND
V
V
C0
ADD
DD
DD
2
C Slave Addresses
A3
Extended Command Mode
D9
A2
D8
Read/Write (R/W) bit.
DEVICE ADDRESS
Write Data Format
A1
D7
0111 000
0111 001
1011 000
1011 001
(A6...A0)
A0
D6
R/W
9