DS15BR400EVK National Semiconductor, DS15BR400EVK Datasheet - Page 8

• Manufacturer Part Number: DS15BR400EVK
• Manufacturer: National Semiconductor

Specifications of DS15BR400EVK

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Application Information
INTERNAL TERMINATIONS
The DS15BR400 has integrated termination resistors on both
the input and outputs. The inputs have a 100Ω resistor across
the differential pair, placing the receiver termination as close
as possible to the input stage of the device. The LVDS outputs
also contain an integrated 100Ω ohm termination resistor, this
resistor is used to minimize the output return loss and does
not take the place of the 100 ohm termination at the inputs to
the receiving device. The integrated terminations improve
signal integrity and decrease the external component count
resulting in space savings. The DS15BR401 has 100Ω output
terminations only.
OUTPUT CHARACTERISTICS
The output characteristics of the DS15BRB400/DS15BR401
have been optimized for point-to-point backplane and cable
applications, and are not intended for multipoint or multidrop
signaling.
POWERDOWN MODE
The PWDN input activates a hardware powerdown mode.
When the powerdown mode is active (PWDN=L), all input and
output buffers and internal bias circuitry are powered off.
When exiting powerdown mode, there is a delay associated
with turning on bandgap references and input/output buffer
circuits as indicated in the LVDS Output Switching Charac-
teristics
PRE-EMPHASIS
Pre-emphasis dramatically reduces ISI jitter from long or
lossy transmission media. One pin is used to select the pre-
emphasis level for all outputs, off or on. The pre-emphasis
boost is approximately 6 dB at 750 MHz.
Pre-emphasis Control Selection Table
PEM
0
1
Pre-Emphasis
Off
On
8
INPUT FAILSAFE BIASING
External pull up and pull down resistors may be used to pro-
vide enough of an offset to enable an input failsafe under
open-circuit conditions. This configuration ties the positive
LVDS input pin to V
LVDS input pin is tied to GND by a pull down resistor. The pull
up and pull down resistors should be in the 5kΩ to 15kΩ range
to minimize loading and waveform distortion to the driver. The
common-mode bias point ideally should be set to approxi-
mately 1.2V. Please refer to application note AN-1194 “Fail-
safe Biasing of LVDS Interfaces” for more information.
DECOUPLING
Each power or ground lead of the DS15BR400 should be
connected to the PCB through a low inductance path. For best
results, one or more vias are used to connect a power or
ground pin to the nearby plane. Ideally, via placement is im-
mediately adjacent to the pin to avoid adding trace induc-
tance. Placing power plane closer to the top of the board
reduces effective via length and its associated inductance.
Bypass capacitors should be placed close to VDD pins. Small
physical size capacitors, such as 0402, X7R, surface mount
capacitors should be used to minimize body inductance of
capacitors. Each bypass capacitor is connected to the power
and ground plane through vias tangent to the pads of the ca-
pacitor. An X7R surface mount capacitor of size 0402 has
about 0.5 nH of body inductance. At frequencies above 30
MHz or so, X7R capacitors behave as low impedance induc-
tors. To extend the operating frequency range to a few hun-
dred MHz, an array of different capacitor values like 100 pF,
1 nF, 0.03 µF, and 0.1 µF are commonly used in parallel. The
most effective bypass capacitor can be built using sand-
wiched layers of power and ground at a separation of 2–3
mils. With a 2 mil FR4 dielectric, there is approximately 500
pF per square inch of PCB.
The center dap of the LLP package housing the DS15BR400
should be connected to a ground plane through an array of
vias. The via array reduces the effective inductance to ground
and enhances the thermal performance of the LLP package.
DD
thru a pull up resistor and the negative