K4H511638C-ZCCC Samsung Semiconductor, K4H511638C-ZCCC Datasheet - Page 2

• Manufacturer Part Number: K4H511638C-ZCCC
• Manufacturer: Samsung Semiconductor
• Type: DDR SDRAMr

Specifications of K4H511638C-ZCCC

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 650ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 215mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

DDR SDRAM 512Mb C-die (x4, x8, x16)
DDR SDRAM
Table of Contents
1.0 Key Features ...............................................................................................................................4
2.0 Ordering Information ...................................................................................................................4
3.0 Operating Frequencies................................................................................................................4
4.0 Pin Description ...........................................................................................................................5
5.0 Package Physical Dimension ....................................................................................................6
6.0 Block Diagram (32Mbit x4 / 16Mbit x8 / 8Mbit x16 I/O x4 Banks).............................................7
7.0 Input/Output Function Description ............................................................................................8
8.0 Command Truth Table.................................................................................................................9
9.0 General Description...................................................................................................................10
10.0 Absolute Maximum Rating .....................................................................................................10
11.0 DC Operating Conditions ........................................................................................................10
12.0 DDR SDRAM Spec Items & Test Conditions .........................................................................11
13.0 Input/Output Capacitance ......................................................................................................11
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12
15.0 DDR SDRAM IDD spec table ..................................................................................................13
16.0 AC Operating Conditions .......................................................................................................14
17.0 AC Overshoot/Undershoot specification for Address and Control Pins ...........................14
18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................15
19.0 AC Timming Parameters & Specifications ...........................................................................16
20.0 System Characteristics for DDR SDRAM ..............................................................................17
21.0 Component Notes ....................................................................................................................18
22.0 System Notes ..........................................................................................................................20
23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
Rev. 1.1 June. 2005