K4M51323LC-DN75000 Samsung Semiconductor, K4M51323LC-DN75000 Datasheet

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K4M51323LC-DN75000

Manufacturer Part Number
K4M51323LC-DN75000
Description
Manufacturer
Samsung Semiconductor
Type
Mobile SDRAMr
Datasheet

Specifications of K4M51323LC-DN75000

Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
7/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
2.5V
Package Type
FBGA
Operating Temp Range
-25C to 85C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
150mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
K4M51323LC - S(D)N/G/L/F
4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-
visions may apply.
FEATURES
• VDD/VDDQ = 2.5V/2.5V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation.
• Special Function Support.
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 90Balls FBGA ( -SXXX -Pb, -DXXX -Pb Free).
ORDERING INFORMATION
- S(D)N/G : Low Power, Extended Temperature(-25°C ~ 85°C)
- S(D)L/F : Low Power, Commercial Temperature(-25°C ~ 70°C)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
Address configuration
clock.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
K4M51323LC-S(D)N/G/L/F7L
K4M51323LC-S(D)N/G/L/F75
Organization
Part No.
16Mx32
*1
133MHz(CL=3), 111MHz(CL=2)
133MHz(CL=3), 83MHz(CL=2)
BA0,BA1
Bank
Max Freq.
GENERAL DESCRIPTION
rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
1
The K4M51323LC is 536,870,912 bits synchronous high data
A0 - A12
Row
Interface
LVCMOS
Mobile-SDRAM
Column Address
90 FBGA Pb
A0 - A8
(Pb Free)
Package
March 2006

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K4M51323LC-DN75000 Summary of contents

Page 1

... GENERAL DESCRIPTION The K4M51323LC is 536,870,912 bits synchronous high data rate Dynamic RAM organized 4,196,304 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technol- ogy ...

Page 2

... K4M51323LC - S(D)N/G/L/F FUNCTIONAL BLOCK DIAGRAM Bank Select CLK ADD LCKE LRAS LCBR CLK CKE CS Data Input Register Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register RAS CAS WE 2 Mobile-SDRAM LWCBR LDQM DQM LWE LDQM DQi March 2006 ...

Page 3

... K4M51323LC - S(D)N/G/L/F Package Dimension and Pin Configuration < Bottom View < Top View #A1 Ball Origin Indicator *1 > Pin Name > DQM Symbol 3 Mobile-SDRAM *2 < Top View > 90Ball(6x15) FBGA DQ26 DQ24 DQ28 DDQ SSQ DDQ V DQ27 DQ25 DQ22 SSQ V DQ29 DQ30 DQ17 SSQ V DQ31 NC NC ...

Page 4

... K4M51323LC - S(D)N/G/L/F ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage temperature Power dissipation Short circuit current NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. ...

Page 5

... K4M51323LC - S(D)N/G/L/F DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to V Parameter Symbol Operating Current I CC1 (One Bank Active Precharge Standby Current in power-down mode 2PS CKE & CLK ≤ Precharge Standby Current in non power-down mode I 2NS Active Standby Current in power-down mode 3PS CKE & CLK ≤ V ...

Page 6

... K4M51323LC - S(D)N/G/L/F AC OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition VDDQ 500Ω Output 500Ω Figure 1. DC Output Load Circuit = 2.5V ± 0.2V, T ...

Page 7

... K4M51323LC - S(D)N/G/L/F OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col ...

Page 8

... K4M51323LC - S(D)N/G/L/F AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CLK cycle time CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z NOTES : 1 ...

Page 9

... K4M51323LC - S(D)N/G/L/F SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Auto Precharge Enable ...

Page 10

... K4M51323LC - S(D)N/G/L/F A. MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Normal MRS BA0 ~ BA1 Address A12 ~ A10/AP "0" Setting for Function Normal MRS Normal MRS Mode Test Mode A8 A7 Type Mode Register Set Reserved Reserved Reserved 0 Write Burst Length 1 A9 ...

Page 11

... K4M51323LC - S(D)N/G/L/F Partial Array Self Refresh 1. In order to save power consumption, Mobile SDRAM has PASR option. 2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array. BA1=0 BA1=0 BA0=0 BA0=1 BA1=1 BA1=1 BA0=0 BA0=1 ...

Page 12

... K4M51323LC - S(D)N/G/L/F C. BURST SEQUENCE 1. BURST LENGTH = 4 Initial Address BURST LENGTH = 8 Initial Address Sequential Sequential Mobile-SDRAM Interleave Interleave March 2006 ...

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