BOXD865GLCL Intel, BOXD865GLCL Datasheet - Page 67

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BOXD865GLCL

Manufacturer Part Number
BOXD865GLCL
Description
Manufacturer
Intel
Datasheet

Specifications of BOXD865GLCL

Lead Free Status / Rohs Status
Supplier Unconfirmed
Table 25.
Note:
NOTE
In PIC mode, the ICH5 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6,
7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a
unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or
more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 24 for the
allocation of PIRQ lines to IRQ signals in APIC mode.
PCI Interrupt Source
AGP connector
ICH5 USB UHCI controller 1 INTA
SMBus controller
ICH5 USB UHCI controller 2
AC ’97 ICH5 Audio
ICH5 LAN
ICH5 USB UHCI controller 3
ICH5 USB UHCI controller 4 INTA
ICH5 USB 2.0 EHCI controller
PCI bus connector 1
PCI bus connector 2
PCI bus connector 3
PCI bus connector 4
PCI bus connector 5
PCI bus connector 6
Serial ATA
Desktop Board D865GBF only
PCI Interrupt Routing Map
(Note)
(Note)
(Note)
PIRQA
INTA
INTD
INTC
PIRQB
INTB
INTB
INTB
INTA
INTA
PIRQC
INTC
INTB
INTB
INTA
ICH5 PIRQ Signal Name
PIRQD
INTB
INTC
INTA
PIRQE
INTA
INTD
INTC
INTD
INTB
PIRQF
INTA
INTB
INTC
INTD
INTA
Technical Reference
PIRQG
INTB
INTA
INTD
INTC
PIRQH
INTD
INTC
INTD
INTB
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