CY7C464-40PC Cypress Semiconductor Corp, CY7C464-40PC Datasheet - Page 8

• Manufacturer Part Number: CY7C464-40PC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C464-40PC

• Configuration: Dual
• Density: 288Kb
• Access Time (max): 40ns
• Word Size: 9b
• Organization: 32Kx9
• Sync/async: Asynchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PDIP
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 70mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

Architecture
Resetting the FIFO
Upon power up, the FIFO must be reset with a master reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF), and Full flags (FF) being HIGH. Read (R) and write
(W) must be HIGH t
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs t
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LOW tWHF after the falling edge of W following the FIFO ac-
tually being half full. Therefore, the HF is active once the FIFO
is filled to half its capacity plus one word. HF will remain LOW
while less than one half of total memory is available for writing.
The LOW-to-HIGH transition of HF occurs t
edge of R when the FIFO goes from half full +1 to half full. HF
is available in standalone and width expansion modes. FF
goes LOW tWFF after the falling edge of W, during the cycle
in which the last available location is filled. Internal logic pre-
vents overrunning a full FIFO. Writes to a full FIFO are ignored
and the write pointer is not incremented. FF goes HIGH tRFF
after a read from a full FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Q
tween read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. When the FIFO is empty, the
outputs are in a high-impedance state. Reads to an empty
FIFO are ignored and do not increment the read pointer. From
the empty condition, the FIFO can be read t
write.
0
RPW
Q
8
) are in a high-impedance condition be-
/t
WPW
0
D
before and tRMR after the rising
8
) t
SD
before and t
WEF
RHF
WEF
after the rising
after the first
after a valid
HD
after the
8
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. The retransmit
(RT) input is active in the standalone and width expansion
modes. The retransmit feature is intended for use when a
number of writes equal-to-or-less-than the depth of the FIFO
have occurred since the last MR cycle. A LOW pulse on RT
resets the internal read pointer to the first physical location of
the FIFO. R and W must both be HIGH while and tRTR after
retransmit is LOW. With every read cycle after retransmit, pre-
viously accessed data is read and the read pointer increment-
ed until equal to the write pointer. Full, Half Full, and Empty
flags are governed by the relative locations of the read and
write pointers and are updated during a retransmit cycle. Data
written to the FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding
expansion in (XI) and tying first load (FL) to V
cycle. FIFOs can be expanded in width to provide word widths
greater than nine in increments of nine. During width expan-
sion mode, all control line inputs are common to all devices,
and flag outputs from any device can be monitored.
Depth Expansion Mode ( see Figure 1 )
Depth expansion mode is entered when, during a MR cycle,
expansion out (XO) of one device is connected to expansion
in (XI) of the next device, with XO of the last device connected
to XI of the first device. In the depth expansion mode, the first
load (FL) input, when grounded, indicates that this is the first
part to be loaded. All other devices must have this pin HIGH.
To enable the correct FIFO, XO is pulsed LOW when the last
physical location of the previous FIFO is written to and is
pulsed LOW again when the last physical location is read.
Only one FIFO is enabled for read and one is enabled for write
at any given time. All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and
width. Consequently, any depth or width FIFO can be created
with word widths in increments of nine. When expanding in
depth, a composite FF is created by ORing the FFs together.
Likewise, a composite EF is created by ORing EFs together.
HF and RT functions are not available in depth expansion
mode.
CY7C460
CY7C462
CY7C464
CC
prior to a MR