K4H511638C-ZCB3 Samsung Semiconductor, K4H511638C-ZCB3 Datasheet - Page 4
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K4H511638C-ZCB3
Manufacturer Part Number
K4H511638C-ZCB3
Description
Manufacturer
Samsung Semiconductor
Type
DDR SDRAMr
Datasheet
1.K4H511638C-ZCB3.pdf
(24 pages)
Specifications of K4H511638C-ZCB3
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
185mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
K4H511638C-ZCB3
Manufacturer:
SAMSUNG
Quantity:
13
1.0 Key Features
2.0 Ordering Information
3.0 Operating Frequencies
DDR SDRAM 512Mb C-die (x4, x8, x16)
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA
•
RoHS compliant
-. Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
K4H510438C-ZC/LCC
K4H510838C-ZC/LCC
K4H511638C-ZC/LCC
K4H510438C-ZC/LB3
K4H510838C-ZC/LB3
K4H511638C-ZC/LB3
Part No.
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
Speed @CL3
Pb-Free
package
128M x 4
32M x 16
64M x 8
Org.
CC(DDR400@CL=3)
CC(DDR400@CL=3)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
166MHz
200MHz
3-3-3
Max Freq.
-
Interface
SSTL2
SSTL2
SSTL2
B3(DDR333@CL=2.5)
Rev. 1.1 June. 2005
133MHz
166MHz
2.5-3-3
DDR SDRAM
-
60ball FBGA
60ball FBGA
60ball FBGA
Package