MF10ACWM National Semiconductor, MF10ACWM Datasheet - Page 8

• Manufacturer Part Number: MF10ACWM
• Manufacturer: National Semiconductor

Specifications of MF10ACWM

• Architecture: Switched Capacitor
• Filter Type: Universal
• Cutoff Frequency: 30KHz
• Dual Supply Voltage (typ): ±5V
• Power Supply Requirement: Single/Dual
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: SOIC W
• Lead Free Status / Rohs Status: Not Compliant

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Pin Descriptions
LP(1,20), BP(2,19), N/AP/HP(3,18)
INV(4,17)
S1(5,16)
S
V
V
LSh(9)
1.0 Definition of Terms
f
10 or 11.
f
pole pair. f
MF10, and is the frequency of maximum bandpass gain.
( Figure 1 )
f
notch outputs.
f
pair, if any. If f
observed as the frequency of a notch at the allpass output.
( Figure 10 )
Q: “quality factor” of the 2nd order filter. Q is measured at the
bandpass outputs of the MF10 and is equal to f
CLK
O
notch
z
A/B
A
A
: the center frequency of the second order complex zero
: center frequency of the second order function complex
+
−
(7),V
(14), V
(6)
: the frequency of the external clock signal applied to pin
: the frequency of minimum (ideally zero) gain at the
D
+
D
(8)
O
−
(13)
is measured at the bandpass outputs of the
z
is different from f
The second order lowpass, bandpass
and notch/allpass/highpass outputs.
These outputs can typically sink 1.5 mA
and source 3 mA. Each output typically
swings to within 1V of each supply.
The inverting input of the summing
op-amp of each filter. These are high
impedance inputs, but the non-inverting
input is internally tied to AGND, making
INV
junctions
inputs).
S1 is a signal input pin used in the
allpass filter configurations (see modes
4 and 5). The pin should be driven with
a source impedance of less than 1 k .
If S1 is not driven with a signal it should
be tied to AGND (mid-supply).
This pin activates a switch that con-
nects one of the inputs of each filter’s
second summer to either AGND (S
tied to V
(S
ity needed for configuring the filter in its
various modes of operation.
Analog positive supply and digital posi-
tive supply. These pins are internally
connected through the IC substrate and
therefore V
rived from the same power supply
source. They have been brought out
separately so they can be bypassed by
separate capacitors, if desired. They
can be externally tied together and by-
passed by a single capacitor.
Analog and digital negative supplies.
The same comments as for V
V
Level shift pin; it accommodates vari-
ous clock levels with dual or single sup-
ply operation. With dual
the MF10 can be driven with CMOS
clock levels (
should be tied to the system ground. If
the same supplies as above are used
D
A/B
+
A
apply here.
tied to V
and INV
−
) or to the lowpass (LP) output
(low
O
A
+
and if Q
+
±
B
and V
). This offers the flexibil-
5V) and the LSh pin
behave like summing
impedance,
Z
D
+
is high, it can be
should be de-
±
5V supplies,
O
divided by
A
current
+
and
A/B
8
CLKA(10),
50/100/CL(12)
AGND(15)
the −3 dB bandwidth of the 2nd order bandpass filter ( Figure
1 ). The value of Q determines the shape of the 2nd order
filter responses as shown in Figure 6 .
Q
if any. Q
written:
where Q
H
OBP
Z
: the quality factor of the second order complex zero pair,
: the gain (in V/V) of the bandpass output at f = f
Z
Z
= Q for an all-pass response.
is related to the allpass characteristic, which is
but only TTL clock levels, derived from
0V to +5V supply, are available, the
LSh pin should be tied to the system
ground. For single supply operation (0V
and +10V) the V
connected to the system ground, the
AGND pin should be biased at +5V and
the LSh pin should also be tied to the
system ground for TTL clock levels.
LSh should be biased at +5V for CMOS
clock levels in 10V single-supply
applications.
CLKB(11)
Clock inputs for each switched capaci-
tor filter building block. They should
both be of the same level (TTL or
CMOS). The level shift (LSh) pin de-
scription discusses how to accommo-
date their levels. The duty cycle of the
clock should be close to 50% especially
when clock frequencies above 200 kHz
are used. This allows the maximum
time for the internal op-amps to settle,
which yields optimum filter operation.
By
clock-to-filter-center-frequency ratio is
obtained. Tying this pin at mid-supplies
(i.e. analog ground with dual supplies)
allows the filter to operate at a 100:1
clock-to-center-frequency ratio. When
the pin is tied low (i.e., negative supply
with dual supplies), a simple current
limiting circuit is triggered to limit the
overall supply current down to about
2.5 mA. The filtering action is then
aborted.
This is the analog ground pin. This pin
should be connected to the system
ground for dual supply operation or bi-
ased to mid-supply for single supply
operation. For a further discussion of
mid-supply biasing techniques see the
Applications Information (Section 3.2).
For optimum filter performance a
“clean” ground must be provided.
tying
this
A
−
pin
, V
D
−
high
pins should be
a
O
50:1
.