CY7C4291-15JC Cypress Semiconductor Corp, CY7C4291-15JC Datasheet
CY7C4291-15JC
Specifications of CY7C4291-15JC
Related parts for CY7C4291-15JC
CY7C4291-15JC Summary of contents
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... LOGIC THREE-STATE OUTPUT REGISTER Q 0–8 Cypress Semiconductor Corporation Document #: 38-06007 Rev. *C CY7C4281 CY7C429164K/128K x 9 Deep Sync FIFOs 64K/128K x 9 Deep Sync FIFOs • Pb-Free Packages Available Functional Description The CY7C4281/91 memories with clocked read and write interfaces. All are nine bits wide ...
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... When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected HIGH, the FIFO’s outputs are in High Z (high-impedance) state. CY7C4291 128k x 9 32-pin PLCC 7C4281/91-10 100 0.5 8 Commercial 40 Industrial 45 CY7C4281 CY7C4291 7C4281/91-15 7C4281/91-25 Unit 66.7 40 MHz ...
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... Default Value = 000h outputs 0– Full Offset (LSB) Reg Default Value = 007h 8 7 outputs 0–8 Default Value = 000h Figure 1. Offset Register Location and Default Values CY7C4281 CY7C4291 128K× Empty Offset (LSB) Reg. Default Value = 007h 0 8 (MSB) (MSB) Default Value = 000h 0 8 ...
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... Empty Offset ( default value Full Offset ( default value). Document #: 38-06007 Rev. *C and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4281 (64K-m) and CY7C4291 (128K-m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. ...
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... Figure 2. Block Diagram of 64k x 9/128k x 9 Deep Sync FIFO Memory Used in a Width Expansion Configuration Document #: 38-06007 Rev. *C RESET (RS) 9 CY7C4281/ Read Enable 2 (REN2) CY7C4281 CY7C4291 READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE(PAE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF) #2 DATA OUT ( Page ...
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... CC Com’l Ind Com’l Ind Test Conditions ° MHz 5.0V CC [9, 10] 3.0V R2 GND 680Ω ≤ 1.91V . CY7C4281 CY7C4291 + 0.5V CC [4] Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° −40 5V ± 10 +85 C 7C42X1−15 7C42X1−25 Max. Min. Max. ...
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... Almost-Empty Flag and Almost-Full Flag Notes: 11. Pulse widths less than minimum values are not allowed. 12. Values guaranteed by design, not currently tested. Document #: 38-06007 Rev. *C 7C42X1-10 7C42X1-15 Min. Max. Min. 100 4.5 4.5 3 0 [12 [12 CY7C4281 CY7C4291 7C42X1-25 Max. Min. Max. Unit 66.7 40 MHz ...
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... CLKL NO OPERATION t REF t REF t A VALID DATA t OE [14] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4281 CY7C4291 NO OPERATION NO OPERATION t OHZ Page [+] Feedback ...
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... Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. Document #: 38-06007 Rev RSR RSS t t RSR RSS t t RSS RSR t RSF t RSF t RSF CY7C4281 CY7C4291 [16 Page [+] Feedback ...
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... The Latency Timing applies only at the Empty Boundary (EF = LOW). SKEW1 19. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06007 Rev [18] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW1 CY7C4281 CY7C4291 [19 (maximum) = either 2 FRL CLK SKEW1 CLK Page [+] Feedback ...
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... WEN1 t ENS t t ENS ENH WEN2 (if applicable) [18] t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06007 Rev DATA WRITE 2 t ENS t ENS REF REF SKEW2 t A CY7C4281 CY7C4291 t ENH t ENH [18] t FRL t REF DATA READ Page [+] Feedback ...
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... If a read is performed on this rising edge of the read clock, there will be Empty + (n −1) words in the FIFO when PAE goes LOW. Document #: 38-06007 Rev SKEW1 DATA WRITE t WFF DATA READ t CLKL t ENS ENH t ENS ENH Note 21 [20] t PAE t ENS CY7C4281 CY7C4291 NO WRITE [13] DATA WRITE t WFF t ENH t ENS t A NEXT DATA READ WORDS Note 22 IN FIFO t PAE t t ENS ENH Page [+] Feedback ...
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... ENH (FULL −M) WORDS t SKEW2 t ENS t CLKL t ENH t DH PAE OFFSET PAF OFFSET LSB MSB , then PAF may not change state until the next WCLK. SKEW2 CY7C4281 CY7C4291 [25] IN FIFO [26] t PAF t t ENS ENH PAF OFFSET LSB MSB Page [+] Feedback ...
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... Speed (ns) Ordering Code 10 CY7C4281-10JC CY7C4281-10JI 15 CY7C4281-15JC 25 CY7C4281-25JC 128K x 9 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4291-10JC CY7C4291-10JXC CY7C4291-10JI 15 CY7C4291-15JC CY7C4291-15JXC 25 CY7C4291-25JC Document #: 38-06007 Rev CLKL t ENH t A UNKNOWN PAE OFFSET LSB PAE OFFSET MSB Package Package Name Type J65 32-Lead Plastic Leaded Chip Carrier ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 32-Lead Plastic Leaded Chip Carrier J65 CY7C4281 CY7C4291 51-85002-*B Page [+] Feedback ...
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... Document History Page Document Title: CY7C4281, CY7C4291 64K/128K X 9 Deep Sync FIFOs Document Number: 38-06007 Orig. of REV. ECN NO. Issue Date Change ** 106468 07/12/01 *A 122259 12/26/02 *B 127854 08/22/03 *C 386004 See ECN Document #: 38-06007 Rev. *C Description of Change SZV Change from Spec number: 38-00587 to 38-06007 ...