MT46H4M32LFB5-6:K Micron Technology Inc, MT46H4M32LFB5-6:K Datasheet - Page 65

• Manufacturer Part Number: MT46H4M32LFB5-6:K
• Description: IC SDRAM 128MB 166MHZ 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr
• Series: -r

Specifications of MT46H4M32LFB5-6:K

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 100mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / Rohs Status: Compliant

Figure 28: READ-to-PRECHARGE
PDF: 09005aef8331b3e9
128mb_mobile_ddr_sdram_t35m.pdf - Rev. F 03/10 EN
Command
Command
Address
Address
DQ4
DQS
DQS
DQ
CK#
CK#
CK
CK
4
Notes:
Banka,
Col n
Banka,
Col n
READ
READ
T0
T0
1. BL = 4, or an interrupted burst of 8 or 16.
2. PRE = PRECHARGE command.
3. ACT = ACTIVE command.
4. D
5. Shown with nominal
6. READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out.
7. A READ command with auto precharge enabled, provided
1
1
cause a precharge to be performed at x number of clock cycles after the READ com-
mand, where x = BL/2.
OUT
n = data-out from column n.
CL = 2
NOP
NOP
T1
T1
CL = 3
T1n
T1n
D
(a or all)
(a or all)
t
Bank a,
Bank a,
AC,
OUT
T2
T2
PRE
PRE
t
2
65
2
DQSCK, and
D
T2n
T2n
OUT
128Mb: x16, x32 Mobile LPDDR SDRAM
D
OUT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
D
T3
NOP
T3
NOP
OUT
t
DQSQ.
D
Don’t Care
OUT
T3n
t
t
T3n
D
RP
RP
OUT
D
OUT
T4
T4
NOP
NOP
D
OUT
t
RAS (MIN) is met, would
Transitioning Data
© 2007 Micron Technology, Inc. All rights reserved.
READ Operation
Bank a,
Bank a,
T5
T5
ACT
Row
ACT
Row
3
3