CY7C4245-10AC Cypress Semiconductor Corp, CY7C4245-10AC Datasheet - Page 15

• Manufacturer Part Number: CY7C4245-10AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4245-10AC

• Configuration: Dual
• Density: 72Kb
• Access Time (max): 8ns
• Word Size: 18b
• Organization: 4Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 45mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

every valid read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal
to the write pointer. Flags are governed by the relative loca-
tions of the read and write pointers and are updated during a
Table 2. Flag Truth Table.
Width Expansion Configuration
The CY7C42X5 can be expanded in width to provide word
widths greater than 18 in increments of 18. During width ex-
pansion mode all control line inputs are common and all flags
Figure 1. Block Diagram of 64x36/256 x 36/512 x 36/1024 x 36/2048 x 36/4096 x 36 Synchronous FIFO Memory Used in a
0
1 to n
(n+1) to 32
33 to (64 – (m+1))
(64 – m)
64
0
1 to n
(n+1) to 512
513 to (1024 – (m+1))
(1024 – m)
1024
Notes:
37. n = Empty Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127).
38. m = Full Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127).
FULL FLAG (FF)
PROGRAMMABLE(PAE)
7C4425 - 64 x 18
7C4225 - 1K x 18
DATA IN (D)
WRITECLOCK (WCLK)
WRITEENABLE (WEN)
HALF FULL FLAG (HF)
[37
[37]
[38]
[38]
to 63
to 1023
LOAD (LD)
36
18
Number of Words in FIFO
Number of Words in FIFO
0
1 to n
(n+1) to 128
129 to (256 – (m+1))
(256 – m)
256
0
1 to n
(n+1) to 1024
1025 to (2048 – (m+1))
(2048 – m)
2048
7C4205 - 256 x 18
7C4235 - 2K x 18
FF
[37]
[37]
RESET (RS)
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
[38]
[38]
to 255
to 2047
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
Width Expansion Configuration
EF
FIRST LOAD (FL)
18
0
1 to n
(n+1) to 256
257 to (512 – (m+1))
(512 – m)
512
0
1 to n
(n+1) to 2048
2049 to (4096 – (m+1))
(4096 – m)
4096
7C4215 - 512 x 18
7C4245 - 4K x 18
[37]
[37]
15
18
[38]
retransmit cycle. Data written to the FIFO after activation of RT
are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
are available. Empty (Full) flags should be created by ANDing
the Empty (Full) flags of every FIFO. This technique will avoid
ready data from the FIFO that is “staggered” by one clock cycle
due to the variations in skew between RCLK and WCLK.
Figure 1 demonstrates a 36-word width by using two CY7C42X5.
[38]
to 511
to 4095
FF
RESET (RS)
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
FF
FF
H
H
H
H
H
H
H
H
H
H
L
L
EF
CY7C4425/4205/4215
CY7C4225/4235/4245
PAF
PAF
18
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUTENABLE (OE)
PROGRAMMABLE(PAF)
H
H
H
H
H
H
H
H
L
L
L
L
DATA OUT (Q)
HF
HF
H
H
H
H
H
H
L
L
L
L
L
L
EMPTYFLAG (EF)
42X5–24
PAE
PAE
H
H
H
H
H
H
H
H
L
L
L
L
36
EF
EF
H
H
H
H
H
H
H
H
H
H
L
L