M68EML08JLJK Freescale Semiconductor, M68EML08JLJK Datasheet - Page 25

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M68EML08JLJK

Manufacturer Part Number
M68EML08JLJK
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of M68EML08JLJK

Lead Free Status / Rohs Status
Not Compliant
User’s Manual
MOTOROLA
Pin
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
11
1
2
3
4
5
6
7
8
9
Table 3-1 Logic Analyzer Connector (P1) Signal Descriptions
Mnemonic
SCLK
LA15
LA14
LA13
LA12
LA10
LA11
GND
GND
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W
LA9
LA8
LA7
LA6
LA5
LA4
LA3
LIR
Support Information
GROUND
Address bus bit 15 — MCU output address bus
Data bus bit 7 — MCU bidirectional data bus
Address bus bit 15 — MCU output address bus
Data bus bit 6 — MCU bidirectional data bus
Address bus bit 13 — MCU output address bus
Data bus bit 5 — MCU bidirectional data bus
Address bus bit 12 — MCU output address bus
Data bus bit 4 — MCU bidirectional data bus
Address bus bit 11 — MCU output address bus
Data bus bit 3 — MCU bidirectional data bus
Address bus bit 10 — MCU output address bus
Data bus bit 2 — MCU bidirectional data bus
Address bus bit 9 — MCU output address bus
Data bus bit 1 — MCU bidirectional data bus
Address bus bit 8 — MCU output address bus
Data bus bit 0 — MCU bidirectional data bus
Address bus bit 7 — MCU output address bus.
Load instruction register — Active-low output signal, asserted
when an instruction starts
Address bus bit 6 — MCU output address bus
Read/Write — Output signal that indicates the direction of data
transfer
Address bus bit 5 — MCU output address bus
GROUND
Address bus bit 4 — MCU output address bus
System clock — Internally generated output clock signal used
as a timing reference
Address bus bit 3 — MCU output address bus
M68EML08JLJK Emulation Module - Version 1.0
Signal Description
Logic Analyzer Connector (P1)
Support Information
25