CY7C4215-10AC Cypress Semiconductor Corp, CY7C4215-10AC Datasheet
CY7C4215-10AC
Specifications of CY7C4215-10AC
Related parts for CY7C4215-10AC
CY7C4215-10AC Summary of contents
Page 1
... Synchronous FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memories • (CY7C4425) • 256 x 18 (CY7C4205) • 512 x 18 (CY7C4215) • (CY7C4225) • (CY7C4235) • (CY7C4245) • High-speed 100-MHz operation (10 ns read/write cycle time) • Low power (I =45 mA) CC • ...
Page 2
... GND GND 42x5–2 2 CY7C4425/4205/4215 CY7C4225/4235/4245 FLAG PROGRAM REGISTER FF EF FLAG PAE LOGIC PAF SMODE READ POINTER READ CONTROL 42X5–1 RCLK REN TQFP Top View CY7C4425 43 6 CY7C4205 42 7 CY7C4215 41 8 CY7C4225 40 9 CY7C4235 CY7C4245 GND GND GND 42X5–3 ...
Page 3
... CY7C4215 CY7C4225 512 68-pin PLCC 68-pin PLCC 64-pin TQFP 64-pin TQFP (10x10/14x14) (10x10/14x14) I Data inputs for an 18-bit bus Data outputs for an 18-bit bus I Enables the WCLK input I Enables the RCLK input I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full ...
Page 4
Pin Definitions (continued) Signal Name Description I/O RXI Read Expansion Input RXO Read Expansion Output RS Reset OE Output Enable V /SMODE Synchronous CC Almost Empty/ Almost Full Flags Maximum Ratings (Above which the useful life may be impaired. For ...
Page 5
Capacitance Parameter Description C Input Capacitance IN C Output Capacitance OUT AC Test Loads and Waveforms R11.1K 5V OUTPUT C L INCLUDING JIG AND SCOPE Equivalent to: THÉ EVENIN EQUIVALENT 410 OUTPUT Notes: 7. Tested initially and after any ...
Page 6
Switching Characteristics Over the Operating Range (continued) Parameter Description t Clock to Programmable Almost-Full Flag PAFsynch (Synchronous mode Clock to Programmable Almost-Empty Flag PAEasynch (Asynchronous mode Clock to Programmable Almost-Full Flag PAEsynch (Synchronous mode, V ...
Page 7
Switching Waveforms (continued) Read Cycle Timing RCLK t t ENS ENH REN EF Q – OLZ OE WCLK WEN [15] Reset Timing RS REN, WEN, LD EF,PAE FF,PAF Notes: 14. .t ...
Page 8
Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLK –D D (FIRSTVALID WRITE ENS WEN t SKEW2 RCLK EF REN Q – Empty Flag ...
Page 9
Switching Waveforms (continued) Full Flag Timing NO WRITE WCLK [13] t SKEW1 D – WFF FF WEN RCLK t ENS REN LOW OE Q –Q DATA IN OUTPUT REGISTER 0 17 Half-Full Flag Timing t CLKH WCLK ...
Page 10
Switching Waveforms (continued) Programmable Almost Empty Flag Timing t CLKH WCLK WEN [19] ] PAE RCLK REN Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW) t CLKH WCLK WEN WEN2 PAE t SKEW3 RCLK REN Notes: ...
Page 11
... CY7C4425, 256 – m words inCY7C4205, 512 – m word in CY7C4215. 1024 – m words in CY7C4225, 2048 – m words in CY7C4235, and 4096 – m words in CY7C4245. 26. 64 – words in CY7C4425, 256 – words in CY7C4205, 512 – words in CY7C4215, 1024 – CY7C4225, 2048 – CY74235, and 4096 – words in CY7C4245. ...
Page 12
Switching Waveforms (continued) Write Programmable Registers t CLK t CLKH WCLK t ENS LD t ENS WEN – Read Programmable Registers t CLK t CLKH RCLK t ENS LD t ENS WEN Q –Q 0 ...
Page 13
Switching Waveforms (continued) Read Expansion Out Timing t WCLK RXO t ENS REN Write Expansion In Timing WXI WCLK Read Expansion In Timing RXI RCLK [33, 34, 35] Retransmit Timing FL/RT REN/WEN EF/FF and all async flags HF/PAE/PAF Notes: 32. ...
Page 14
Architecture The CY7C42X5 consists of an array words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, ...
Page 15
... Notes: 37 Empty Offset (Default Values: CY7C4425 CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127). 38 Full Offset (Default Values: CY7C4425 CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127). Width Expansion Configuration The CY7C42X5 can be expanded in width to provide word widths greater than 18 in increments of 18. During width ex- ...
Page 16
Depth Expansion Configuration (with Programmable Flags) The CY7C42X5 can easily be adapted to applications requir- ing more than 64/256/512/1024/2048/4096 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maxi- mum depth is limited only by signal loading. Follow ...
Page 17
Typical AC and DC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 V =3. =25 C 0.8 A f=100 MHz 0 4.5 5.5 SUPPLY VOLTAGE (V) NORMALIZED t vs.SUPPLY A VOLTAGE 1.2 T =25 ...
Page 18
Ordering Information Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4425-10AC CY7C4425-10ASC CY7C4425-10JC CY7C4425-10AI CY7C4425-10ASI CY7C4425-10JI 15 CY7C4425-15AC CY7C4425-15ASC CY7C4425-15JC CY7C4425-15AI CY7C4425-15ASI CY7C4425-15JI 25 CY7C4425-25AC CY7C4425-25ASC CY7C4425-25JC CY7C4425-25AI CY7C4425-25ASI CY7C4425-25JI 35 CY7C4425-35AC CY7C4425-35ASC CY7C4425-35JC CY7C4425-35AI CY7C4425-35ASI CY7C4425-35JI Package ...
Page 19
Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4205-10AC CY7C4205-10ASC CY7C4205-10JC CY7C4205-10AI CY7C4205-10ASI CY7C4205-10JI 15 CY7C4205-15AC CY7C4205-15ASC CY7C4205-15JC CY7C4205-15AI CY7C4205-15ASI CY7C4205-15JI 25 CY7C4205-25AC CY7C4205-25ASC CY7C4205-25JC CY7C4205-25AI CY7C4205-25ASI CY7C4205-25JI 35 CY7C4205-35AC CY7C4205-35ASC CY7C4205-35JC CY7C4205-35AI CY7C4205-35ASI CY7C4205-35JI Package Package Name ...
Page 20
... Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4215-10AC CY7C4215-10ASC CY7C4215-10JC CY7C4215-10AI CY7C4215-10ASI CY7C4215-10JI 15 CY7C4215-15AC CY7C4215-15ASC CY7C4215-15JC CY7C4215-15AI CY7C4215-15ASI CY7C4215-15JI 25 CY7C4215-25AC CY7C4215-25ASC CY7C4215-25JC CY7C4215-25AI CY7C4215-25ASI CY7C4215-25JI 35 CY7C4215-35AC CY7C4215-35ASC CY7C4215-35JC CY7C4215-35AI CY7C4215-35ASI CY7C4215-35JI Package Package Name Type A65 64-Lead 14x14 Thin Quad Flatpack ...
Page 21
Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4225-10AC CY7C4225-10ASC CY7C4225-10JC CY7C4225-10AI CY7C4225-10ASI CY7C4225-10JI 15 CY7C4225-15AC CY7C4225-15ASC CY7C4225-15JC CY7C4225-15AI CY7C4225-15ASI CY7C4225-15JI 25 CY7C4225-25AC CY7C4225-25ASC CY7C4225-25JC CY7C4225-25AI CY7C4225-25ASI CY7C4225-25JI 35 CY7C4225-35AC CY7C4225-35ASC CY7C4225-35JC CY7C4225-35AI CY7C4225-35ASI CY7C4225-35JI Package Package Name ...
Page 22
Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4235-10AC CY7C4235-10ASC CY7C4235-10JC CY7C4235-10AI CY7C4235-10ASI CY7C4235-10JI 15 CY7C4235-15AC CY7C4235-15ASC CY7C4235-15JC CY7C4235-15AI CY7C4235-15ASI CY7C4235-15JI 25 CY7C4235-25AC CY7C4235-25ASC CY7C4235-25JC CY7C4235-25AI CY7C4235-25ASI CY7C4235-25JI 35 CY7C4235-35AC CY7C4235-35ASC CY7C4235-35JC CY7C4235-35AI CY7C4235-35ASI CY7C4235-35JI Package Package Name ...
Page 23
Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4245-10AC CY7C4245-10ASC CY7C4245-10JC CY7C4245-10AI CY7C4245-10ASI CY7C4245-10JI 15 CY7C4245-15AC CY7C4245-15ASC CY7C4245-15JC CY7C4245-15AI CY7C4245-15ASI CY7C4245-15JI 25 CY7C4245-25AC CY7C4245-25ASC CY7C4245-25JC CY7C4245-25AI CY7C4245-25ASI CY7C4245-25JI 35 CY7C4245-35AC CY7C4245-35ASC CY7C4245-35JC CY7C4245-35AI CY7C4245-35ASI CY7C4245-35JI Package Package Name ...
Page 24
Package Diagrams 64-Lead Thin Plastic Quad Flat Pack A65 64-Pin Thin Quad Flat Pack A64 24 CY7C4425/4205/4215 CY7C4225/4235/4245 ...
Page 25
... Plastic Leaded Chip Carrier J81 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...