LTC4259CGW#TR Linear Technology, LTC4259CGW#TR Datasheet
LTC4259CGW#TR
Specifications of LTC4259CGW#TR
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LTC4259CGW#TR Summary of contents
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... APPLICATIO S IP Phone Systems DTE Power Distribution IEEE 802.3af Compliant Systems , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. 802 is a registered trademark of 2 Instutute of Electrical and Electronics Engineers, Inc trademark of Philips Electronics N.V. U ...
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LTC4259 ABSOLUTE AXI U RATI GS (Note 1) Supply Voltages V to DGND .......................................... – 0. AGND ......................................... 0.3V to – 72V EE DGND to AGND (Note 2) .................................... 1V Digital Pins ...
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ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T SYMBOL PARAMETER Gate Driver I GATE Pin Current GON I GATE Pin Current GOFF I GATE Pin Short-Circuit Pull-Down GPD V External Gate Voltage (V – V GATE GATE n Output ...
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LTC4259 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T SYMBOL PARAMETER DC Maximum Current Limit Duty Cycle CLMAX t Disconnect Delay DIS t DC Disconnect Minimum Pulse VMIN Width Sensitivity Timing f Clock Frequency SCLK t ...
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W U TEST PORT GATE n INT Figure 2. Detect, Class and Turn-On Timing in Auto or Semiauto Modes V SENSE n V SENSE n V MIN INT t VMIN ...
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LTC4259 DIAGRA S SCL SDA AD3 AD2 AD1 AD0 START BY MASTER FAULT FRAME 1 SERIAL BUS ADDRESS BYTE SCL SDA AD3 AD2 AD1 AD0 R/W ACK ...
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CTIO S RESET (Pin 1): Chip Reset, Active Low. When the RESET pin is low, the LTC4259 is held inactive with all channels off and all internal registers reset to their power-up states. When RESET ...
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LTC4259 CTIO S SHDN2 (Pin 18): Shutdown Channel 2, Active Low. See SHDN1. SHDN3 (Pin 19): Shutdown Channel 3, Active Low. See SHDN1. SHDN4 (Pin 20): Shutdown Channel 4, Active Low. See SHDN1. AGND (Pin ...
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W TABLE 1. REGISTER AP LTC4259 4259i 9 ...
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LTC4259 U U REGISTER FU CTIO S Interrupt Registers Interrupt (Address 00h): Interrupt Register, Read Only. A transition to logical 1 of any bit in this register will assert the INT pin (Pin 3) if the corresponding bit in the ...
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U U REGISTER FU CTIO S –26V). Bit 5 signals that the V supply has dropped be- DD low the V UVLO threshold. Bit 7 indicates that the DD LTC4259 die temperature has exceeded its thermal shut- down (TSD) limit. ...
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LTC4259 U U REGISTER FU CTIO S Detect/Class Enable (Address 14h): Detection and Clas- sification Enable, Read/Write. The lower four bits of this register enable the detection circuitry at the correspond- ing port if that port is in Auto or ...
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U U APPLICATIO S I FOR ATIO OVERVIEW Over the years, twisted-pair Ethernet has become the most commonly used method for local area networking. The IEEE 802.3 group, the originator of the Ethernet standard, has defined an extension to the ...
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LTC4259 U U APPLICATIO S I FOR ATIO OPERATING MODES Each LTC4259 port can operate in one of four modes: Manual, Semiauto, Auto or Shutdown. The operating mode for a port is set by the appropriate bits in the Operating ...
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U U APPLICATIO S I FOR ATIO 275 25k SLOPE 165 SECOND DETECTION POINT VALID PD 0V-2V VOLTAGE OFFSET Figure 13. PD Detection 17k and 29k (between 19k and 26.5k guaranteed valid PD and report Detect Good (100 ...
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LTC4259 U U APPLICATIO S I FOR ATIO 60 OVER CURRENT 50 40 CLASS 4 CLASS CLASS 2 TYPICAL CLASS 3 CLASS CLASS VOLTAGE (V ) CLASS Figure ...
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U U APPLICATIO S I FOR ATIO Dual-Level Current Limit permitted to draw up to 350mA continuously and up to 400mA for 50ms. The LTC4259 has two correspond- ing current limit thresholds, I (350mA to 400mA, 375mA ...
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LTC4259 U U APPLICATIO S I FOR ATIO Foldback Foldback is designed to limit power dissipation in the MOSFET during short-circuit conditions and during power- up. At low port output voltages, the voltage across the MOSFET is high, and power ...
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U U APPLICATIO S I FOR ATIO Before designing a MOSFET into your system, carefully compare its safe operating area (SOA) with the worst case conditions (like powering on a defective PD) the device will face. Using transient suppressors, polyfuses ...
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LTC4259 U U APPLICATIO S I FOR ATIO 300mV 600mA 250mV 500mA 200mV 400mA 150mV 300mA 100mV 200mA 50mV 100mA 0mV 0mA SENSE n CURRENT DC DIS- CUT LIMIT VOLTAGE R = 0.5 CONNECT ( CUT ...
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U U APPLICATIO S I FOR ATIO When choosing C and C , carefully consider voltage DET PSE derating of the capacitors. Capacitors built around an X7R dielectric will have about 60% of the specified capacitance at their rated voltage. ...
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LTC4259 U U APPLICATIO S I FOR ATIO the OSCIN pin is driven with either a sine wave or a smoothed trapezoid wave, the LTC4259 is able to distin- guish between capacitive impedance and resistive imped- ance on the Power ...
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U U APPLICATIO S I FOR ATIO disconnect itself is a more thorough test of the OSCIN signal. When the OSCIN signal is either absent or cor- rupted, powered channels with AC disconnect enabled (and DC disconnect not enabled) will ...
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LTC4259 U U APPLICATIO S I FOR ATIO V CPU DD SCL SDA TO CONTROLLER SMBELRT GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L 0 200 U1 200 HCPL-063L U3 200 200 0.1 F ...
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U U APPLICATIO S I FOR ATIO The START and STOP Conditions When the bus is idle, both SCL and SDA must be high. A bus master (typically the host system) signals the begin- ning of a communication to a ...
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LTC4259 U U APPLICATIO S I FOR ATIO asserting the INT pin, it acknowledges and sends its 7-bit bus address (010A and a 1 (see Figure 10 While it is sending its ...
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... LTC4259 to make an 802.3af complaint PSE. Each para- graph below addresses a component which is critical for PSE compliance as well as possible pitfalls that can cause a PSE to be noncompliant. For further assistance please contact Linear Technology’s Applications department. L4 100 H R38 510 ...
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LTC4259 U U APPLICATIO S I FOR ATIO Sense Resistors The 0.5 resistors (R ) used to sense the current through S a port affect the current limit and all thresholds for a powered port. An error in the value ...
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U U APPLICATIO S I FOR ATIO handle dissipating at least 0.5W should not be stressed in this application. Other component leakages can have a similar affect on AC disconnect and affect DC disconnect if the leakage becomes more severe. ...
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... In addition, consider checking for IEEE 802.3af compliance after subjecting the PSE to real-world fault conditions: ESD and cable discharge events, shorted ports, connecting to an already powered port, power supply glitches and so on. Linear Technology’s Applica- tions department can also provide additional support. 4259i ...
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PACKAGE DESCRIPTIO 10.668 MIN 0.520 0.0635 RECOMMENDED SOLDER PAD LAYOUT 7.417 – 7.595** (.292 – .299) 0.254 – 0.406 45 (.010 – .016) 0.231 – 0.3175 0.610 – 1.016 (.024 – .040) (.0091 – .0125) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS ...
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... DET 0.22 F 100V X7R D DET BAV19WS D TSS 58V 10k SMAJ58A D AC S1B CONNECTOR 1/2 PULSE H2009 0.01 F 0.01 F 200V 200V 1:1 0.01 F 0.01 F 200V 200V 1000pF 1:1 2000V LT/TP 0803 1K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2003 RJ45 4258 F20 4259i ...