NS7520B-1-I55 Digi International, NS7520B-1-I55 Datasheet - Page 22
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NS7520B-1-I55
Manufacturer Part Number
NS7520B-1-I55
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Specifications of NS7520B-1-I55
Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NS7520B-1-I55
Manufacturer:
VBYONE
Quantity:
880
Company:
Part Number:
NS7520B-1-I55
Manufacturer:
Digi International
Quantity:
10 000
CPU module
The CPU uses an ARM7TDMI core processor. The ARM architecture is based on Reduced Instruction
Set Computer (RISC) principles, which result in high instruction throughput and impressive real-
time interrupt response for a small, cost-effective circuit. For more information about ARM7TDMI,
see the ARM7TDMI Data Sheet from ARM Ltd. (www.arm.com).
GEN module
The GEN module provides the NS7520 with its main system control functions, as well as these
features:
System (SYS) module
The system module provides the system clock
The system control signals determine the basic operation of the chip:
1 8
NS7520 modules
{XTALA1, XTALA2}
{PLLVDD, PLLVSS}
RESET_
{TDI, TDO, TNS,
TRST_, TCK}
{PLLTEST_, BISTEN_,
SCANEN_}
N S 7 5 2 0 m o d u l e s
Signal mnemonic
Two programmable timers with interrupt
One programmable bus-error timer
One programmable watchdog timer
Two 8-bit programmable general-purpose I/O ports
Clock source
PLL power
Chip reset
JTAG interface
Chip mode
Signal name
N S 7 5 2 0 D a t a s h e e t
Operate in one of two ways:
Provide an isolated power supply for the PLL.
Active low signal asserted to initiate a hardware reset of the
chip.
Provide a JTAG interface for the chip. This interface is used
for both boundary scan and ICE control of the internal
processor.
Encoded to determine the chip mode.
Description
(SYS_CLK)
The signals are affixed with a 10-20 MHz parallel mode
quartz crystal or crystal oscillator and the appropriate
components per the component manufacturer.
left open.
XTALA1 is driven with a clock signal and XTALA2 is
0 3 / 2 0 0 6
and system reset
(SYS_RESET)
resources.