STK22C48-P45 Cypress Semiconductor Corp, STK22C48-P45 Datasheet - Page 7

• Manufacturer Part Number: STK22C48-P45
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK22C48-P45

• Word Size: 8b
• Organization: 2Kx8
• Density: 16Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 65mA
• Lead Free Status / Rohs Status: Not Compliant

The STK22C48 has two separate modes of opera-
tion:
mode, the memory operates as a standard fast
static
from
from
this mode
NOISE CONSIDERATIONS
The STK22C48 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between V
V
sible. As with all high-speed
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK22C48 performs a
and G are low and W and HSB are high. The
address specified on pins A
the 2,048 data bytes will be accessed. When the
READ
puts will be valid after a delay of t
#1). If the
be valid at t
cycle #2). The data outputs will repeatedly respond
to address changes within the t
out the need for transitions on any control input pins,
and will remain valid until another address change or
until E or G is brought high, or W or HSB is brought
low.
SRAM WRITE
A
low and HSB is high. The address inputs must be
stable prior to entering the
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ
before the end of a W controlled
before the end of an E controlled
It is recommended that G be kept high during the
entire
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
July 1999
SS
WRITE
, using leads and traces that are as short as pos-
0-7
SRAM
EEPROM
SRAM
will be written into the memory if it is valid t
RAM
is initiated by an address transition, the out-
WRITE
cycle is performed whenever E and W are
READ
SRAM
. In nonvolatile mode, data is transferred
ELQV
mode and nonvolatile mode. In
to
cycle to avoid data bus contention on
to
EEPROM
is initiated by E or G, the outputs will
or at t
functions are disabled.
SRAM
GLQV
(the
(the
, whichever is later (
READ
CMOS
0-10
WRITE
RECALL
WLQZ
STORE
AVQV
determines which of
WRITE
cycle whenever E
after W goes low.
ICs, normal care-
access time with-
AVQV
cycle and must
WRITE
DEVICE OPERATION
operation). In
operation) or
(
.
READ
CAP
or t
SRAM
READ
cycle
DVWH
and
DVEH
3-27
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
be initiated and will take t
If the STK22C48 is in a
power-up
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
AutoStore™ OPERATION
The STK22C48 can be powered in one of three
modes.
During
STK22C48 will draw current from V
capacitor connected to the V
charge will be used by the chip to perform a single
STORE
on the V
automatically disconnect the V
initiate a
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68µF and
220µF (± 20%) rated at 6V should be provided.
In system power mode (Figure 3), both V
V
the 68µF capacitor. In this mode the AutoStore™
function of the STK22C48 will operate on the stored
system charge as power goes down. The user must,
however, guarantee that V
3.6V during the 10ms
If an automatic
then V
V
mode, in which the AutoStore™ function is disabled.
If the STK22C48 is operated in this configuration,
references to V
throughout this data sheet. In this mode,
operations may be triggered with the HSB pin. It is
not permissable to change between these three
options “on the fly”.
CC
CAP
CAP
CAP
or between E and system V
are connected to the + 5V power supply without
< V
(Figure 4). This is the AutoStore™ Inhibit
CCX
operation. After power up, when the voltage
STORE
CAP
RESET
normal
RECALL
can be tied to ground and + 5V applied to
SWITCH
pin drops below V
), an internal
STORE
operation.
CAP
, a
CCX
, the
AutoStore™
once again exceeds the sense
RECALL
should be changed to V
STORE
on power loss is not required,
SRAM
RESTORE
WRITE
CCX
RECALL
cycle will automatically
cycle.
data will be corrupted.
CAP
does not drop below
CAP
CC
to complete.
SWITCH
state at the end of
.
pin from V
pin. This stored
operation,
CCX
request will be
STK22C48
, the part will
to charge a
CCX
CCX
STORE
and
and
the
CAP