MT46V32M16D2TH-7L Micron Technology Inc, MT46V32M16D2TH-7L Datasheet - Page 32

MT46V32M16D2TH-7L

Manufacturer Part Number
MT46V32M16D2TH-7L
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet

Specifications of MT46V32M16D2TH-7L

Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65 – Rev. A; Pub 10/00
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
NOTE: 1. DI b = data-in for column b.
CK#
DM
DM
DM
DQ
DQ
DQ
CK
2. An interrupted burst of 4 or 8 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4. t WTR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would
mask the last two data elements.
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
DI
b
NOP
T1
DI
b
DI
b
WRITE to READ – Interrupting
T1n
NOP
T2
t
WTR
Figure 20
T2n
32
Bank a,
READ
Col n
T3
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CL = 2
CL = 2
CL = 2
T4
NOP
512Mb: x4, x8, x16
TRANSITIONING DATA
T5
NOP
DI
DI
DI
n
n
n
DDR SDRAM
T5n
©2000, Micron Technology, Inc.
ADVANCE
T6
NOP
T6n

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