MT47H16M16BG-3 Micron Technology Inc, MT47H16M16BG-3 Datasheet - Page 104

• Manufacturer Part Number: MT47H16M16BG-3
• Manufacturer: Micron Technology Inc

Specifications of MT47H16M16BG-3

• Lead Free Status / Rohs Status: Compliant

Figure 61: WRITE-to-PRECHARGE
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
Command
Address
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
DQS#
DQS#
DQS#
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
Bank a,
WRITE
Col b
T0
Notes:
WL + t DQSS
WL - t DQSS
WL + t DQSS
NOP
1. Subsequent rising DQS signals must align to the clock within
2. DI b = data-in for column b.
3. Three subsequent elements of data-in are applied in the programmed order following
4. BL = 4, CL = 3, AL = 0; thus, WL = 2.
5.
6. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
7. A10 is LOW with the WRITE command (auto precharge is disabled).
T1
DI b.
t
and WRITE commands may be to different banks, in which case
the PRECHARGE command could be applied earlier.
WR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
T2
DI
b
DI
b
T2n
1
NOP
1
T3
104
1
T3n
T4
NOP
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256Mb: x4, x8, x16 DDR2 SDRAM
T5
NOP
Transitioning Data
t WR
©2003 Micron Technology, Inc. All rights reserved.
t
T6
DQSS.
NOP
t
WR is not required and
(a or all)
T7
Bank,
PRE
Don’t Care
t RP
WRITE