LM555J/NOPB National Semiconductor, LM555J/NOPB Datasheet - Page 8

• Manufacturer Part Number: LM555J/NOPB
• Manufacturer: National Semiconductor

Specifications of LM555J/NOPB

• Lead Free Status / Rohs Status: Compliant

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Applications Information
Figure 13 shows waveforms generated by the linear ramp.
The time interval is given by:
V
TIME = 20 µs/DIV. Middle Trace: Output 5V/Div.
R
R
R
C = 0.01 µF
50% DUTY CYCLE OSCILLATOR
For a 50% duty cycle, the resistors R
nected as in Figure 14 . The time period for the output high is
the same as previous, t
is t
CC
1
2
E
= 47 k
= 100 k
= 2.7 k
2
= 5V
=
Bottom Trace: Capacitor Voltage 1V/Div.
FIGURE 13. Linear Ramp
Top Trace: Input 3V/Div.
1
V
= 0.693 R
BE
0.6V
A
C. For the output low it
A
and R
(Continued)
B
may be con-
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8
Thus the frequency of oscillation is
Note that this circuit will not oscillate if R
R
down to 1/3 V
ADDITIONAL INFORMATION
Adequate power supply bypassing is necessary to protect
associated circuitry. Minimum recommended is 0.1 µF in par-
allel with 1 µF electrolytic.
Lower comparator storage time can be as long as 10 µs
when pin 2 is driven fully to ground for triggering. This limits
the monostable pulse width to 10 µs minimum.
Delay time reset to output is 0.47 µs typical. Minimum reset
pulse width must be 0.3 µs, typical.
Pin 7 current switches within 30 ns of the output (pin 3) volt-
age.
A
because the junction of R
FIGURE 14. 50% Duty Cycle Oscillator
CC
and trigger the lower comparator.
A
and R
B
B
cannot bring pin 2
is greater than 1/2
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