AD660BR Analog Devices Inc, AD660BR Datasheet - Page 15

• Manufacturer Part Number: AD660BR
• Description: IC DAC 16BIT MONO W/VREF 24-SOIC
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD660BR

• Data Interface: Serial
• Rohs Status: RoHS non-compliant
• Settling Time: 6µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 625mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 167kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 4.5V To 5.5V
• Supply Current: 12mA
• Digital Ic Case Style: SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MICROPROCESSOR INTERFACE
AD660 TO MC68HC11 (SPI BUS) INTERFACE
The AD660 interface to the Motorola SPI (serial peripheral
interface) is shown in Figure 17. The MOSI, SCK, and SS pins
of the 68HC11 are respectively connected to the DB0/DB8/SIN,
CS , and LDAC pins of the AD660. The SER pin of the AD660 is
tied low causing the first rank latch to be transparent. The
majority of the interfacing issues are taken care of in the
software initialization. A typical routine such as the one shown
in the Software Initialization Example begins by initializing the
state of the various SPI data and control registers.
The most significant data byte (MSBY) is then retrieved from
memory and processed by the SENDAT subroutine. The SS pin
is driven low by indexing into the PORTD data register and
clearing Bit 5. This causes the 2nd rank latch of the AD660 to
become transparent. The MSBY is then set to the SPI data
register where it is automatically transferred to the AD660.
The HC11 generates the requisite eight clock pulses with data
valid on the rising edges. After the most significant byte is
transmitted, the least significant byte (LSBY) is loaded from
memory and transmitted in a similar fashion. To complete the
transfer, the LDAC pin is driven high, latching the complete
16-bit word into the AD660.
Software Initialization Example
INIT
NEXTPT
SENDAT
WAIT1
WAIT2
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
BSR
JMP
LDY
BCLR
STAA
LDAA
BPL
LDAA
STAA
LDAA
BPL
BSET
RTS
PORTD
#$38
DDRD
#$50
SPCR
MSBY
SENDAT
NEXTPT
#$1000
$08,Y,$20
SPDR
SPSR
WAIT1
LSBY
SPDR
SPSR
WAIT2
$08,Y,$20
#$2F
; SS = I; SCK = 0; MOSI
= I
;SEND TO SPI OUTPUTS
; SS , SCK,MOSI = OUTPUTS
;SEND DATA DIRECTION
INFO
;DABL INTRPTS,SPI IS
MASTER & ON
;CPOL = 0, CPHA = 0,1MHZ
BAUD RATE
;LOAD ACCUM WITH UPPER 8
BITS
;JUMP TO DAC OUTPUT
ROUTINE
;INFINITE LOOP
;POINT AT ON-CHIP
REGISTERS
;DRIVE SS (LDAC) LOW
;SEND MS-BYTE TO SPI
DATA REG
;CHECK STATUS OF SPIE
;POLL FOR END OF X-
MISSION
;GET LOW 8 BITS FROM
MEMORY
;SEND LS-BYTE TO SPI
DATA REG
;CHECK STATUS OF SPIE
;POLL FOR END OF X-
MISSION
;DRIV SS HIGH TO LATCH
DATA
Rev. B | Page 15 of 20
AD660 TO MICROWIRE INTERFACE
The flexible serial interface of the AD660 is also compatible
with the National Semiconductor MICROWIRE™ interface.
The MICROWIRE interface is used on microcontrollers, such
as the COP400 and COP800 series of processors. A generic
interface to the MICROWIRE interface is shown in Figure 18.
The G1, SK, and SO pins of the MICROWIRE interface are respec-
tively connected to the LDAC, CS and DB0/DB8/SIN pins of
the AD660.
AD660 TO ADSP-210x FAMILY INTERFACE
The serial mode of the AD660 minimizes the number of control
and data lines required to interface to digital signal processors
(DSPs) such as the ADSP-210x family. The application in
Figure 19 shows the interface between an ADSP-210x and the
AD660. Both the TFS pin and the DT pins of the ADSP-210x
should be connected to the SER and DB0 pins of the AD660,
respectively. An inverter is required between the SCLK output
and the CS input of the AD660 to ensure that data transmitted
to the DB0 pin is valid on the rising edge of CS .
The serial port (SPORT) of the DSP should be configured for
alternate framing mode so that TFS complies with the word
length framing requirement of SER . Note that the INVTFS bit
in the SPORT control register should be set to invert the TFS
signal so that SER is the correct polarity. The LDAC signal,
which must meet the minimum hold specification of t
easily generated by delaying the rising edge of SER with a
74HC74 flip-flop. The CS signal clocks the flip-flop, resulting
in a delay of approximately one CS clock cycle.
MICROWIRE™
68HC11
Figure 17. AD660 to 68HC11 (SPI) Interface
Figure 18. AD660 to MICROWIRE Interface
MDSI
SCK
SS
SO
SK
G1
DB0/DB8/SIN
CS
LDAC
SER
DB0/DB8/SIN
CS
LDAC
SER
AD660
AD660
AD660
HIGH
, is