AD7742BN Analog Devices Inc, AD7742BN Datasheet - Page 10

• Manufacturer Part Number: AD7742BN
• Manufacturer: Analog Devices Inc

Specifications of AD7742BN

• Converter Function: VFC
• Full Scale Frequency: 2750
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (max): 5.25V
• Single Supply Voltage (min): 4.75V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

AD7741/AD7742
APPLICATIONS
The basic connection diagram for the part is shown in Figure 9.
In the connection diagram shown, the AD7742 analog inputs
are configured as fully differential, bipolar inputs with a gain of
1. A quartz crystal provides the master clock source for the part.
It may be necessary to connect capacitors (C1 and C2 in the
diagram) on the crystal to ensure that it does not oscillate at over-
tones of its fundamental operating frequency. The values of ca-
pacitors will vary depending on the manufacturer’s specifications.
A/D Conversion Techniques Using the AD7741/AD7742
When used as an ADC, VFCs provide certain advantages in-
cluding accuracy, linearity and being inherently monotonic. The
AD7741/AD7742 has a true integrating input which smooths
out noise peaks.
The most popular method of using a VFC in an A/D system is
to count the output pulses of f
Figure 10). This fixed gate interval should be generated by
dividing down the clock input frequency. This ensures that any
errors due to clock jitter or clock frequency drift are eliminated.
The ratio of the f
here, not the absolute value of f
be done by a binary counter where f
Figure 11 shows the waveforms of f
signal. A counter counts the rising edges of f
signal is high. Since the gate interval is not synchronized with
f
on f
OUT
OUT,
, there is a possibility of a counting inaccuracy. Depending
an error of one count may occur.
Figure 9. Basic Connection Diagram
CHANNEL
SELECT
INPUT 1
INPUT 2
DIFF
DIFF
OUT
to the clock frequency is what is important
V
V
V
V
IN
IN
IN
IN
A0
A1
1
2
3
4
CLKIN
C1
OUT
AD7742
OUT
V
+5V
DD
for a fixed gate interval (see
. The frequency division can
CLKIN
CLKIN
PD
REFOUT
, f
UNI/BIP
REFIN
is the CLK input.
OUT
GAIN
GND
f
CLKOUT
C2
OUT
OUT
and the Gate
while the Gate
–10–
The clock frequency and the gate time determine the resolution
of such an ADC. If 12-bit resolution is required and f
5 MHz (therefore, f
time required is calculated as follows:
N counts at Full Scale (2.25 MHz) will take
N is the total number of codes for a given resolution; 4096 for
12 bits
Since T
faster conversion with the same resolution can be performed
with a higher f
feature of the AD7741/AD7742.
If the output frequency is measured by counting pulses gated to
a signal which is derived from the clock, the clock stability is
unimportant and the device simply performs as a voltage-
controlled frequency divider, producing a high resolution ADC.
The inherent monotonicity of the transfer function and wide
range of input clock frequencies allows the conversion time and
resolution to be optimized for specific applications.
There is another parameter is taken into account when choosing
the length of the gate interval. Because the integration period of
the system is equal to the gate interval, any interfering signal can
be rejected by counting for an integer number of periods of the
interfering signal. For example, a gate interval of 100 ms will
give normal-mode rejection of 50 Hz and 60 Hz signals.
Figure 11. Waveforms in an A/D Converter Using a VFC
V
f
GATE
Figure 10. A/D Conversion Using the AD7741 VFC
CLKIN
IN
minimum gate time = (4096/2.25
f
OUT
GATE
(N/2.25
GENERATOR
AD7741
OUT
CLOCK
f
OUT
CLKIN
max. This high f
OUT
max = number of counts at full scale, a
4096x T
10
T
f
6
OUT
GATE
max is 2.25 MHz), the minimum gate
) seconds = minimum gate time.
CLOCK
FREQUENCY
DIVIDER
OUT
10
max (3 MHz) is a main
COUNTER
6
) sec = 1.820 ms.
GATE
SIGNAL
CLKIN
TO P
REV. 0
is