AD7769JP-REEL Analog Devices Inc, AD7769JP-REEL Datasheet - Page 6

• Manufacturer Part Number: AD7769JP-REEL
• Manufacturer: Analog Devices Inc

Specifications of AD7769JP-REEL

• Lead Free Status / Rohs Status: Supplier Unconfirmed

AD7769
PIN FUNCTION DESCRIPTION
Pin
1
2
3–10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
TERMINOLOGY
Relative Accuracy
For an ADC, Relative Accuracy or endpoint nonlinearity is the
maximum deviation, in LSBs, of the ADC’s actual code transi-
tion points from a straight line drawn between the endpoints of
the ADC transfer function, i.e., the 00 to 01 and FE to FF Hex
(01111111 to 11111111 Binary) code transitions.
For a DAC, Relative Accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func-
tion, i.e., those voltages which correspond to codes 00 and FF
Hex.
For the specified input and output ranges, 1 LSB = 19.5 mV,
but will vary with V
1 LSB = 2 V
Mnemonic
V
V
DB7–DB0
INT
CLK
CHA/CHB
DGND
ADC/DAC
WR
RD
CS
V
AGND (ADC)
V
V
V
AGND (DAC)
V
V
V
V
DD
CC
SWING
IN
BIAS
IN
SWING
OUT
BIAS
OUT
SWING
B
A
B
A
(ADC)
(DAC)
(ADC)
(DAC)
/ 256 = FSR / 256.
SWING
. For both DACs and ADC,
Description
+12 V Power Supply. This powers the analog circuitry.
+5 V Power Supply. This powers the logic circuitry.
Input/Output Data Bus. A bidirectional data port from which ADC output data may be read
and to which DAC input data may be written. DB7 is the Most Significant Bit.
Interrupt Output (active low). INT is set high on the falling edge of RD or WR to the ADC
and goes low at the end of a conversion.
Clock input. A clock is required for the ADC. An external TTL-compatible clock may be applied to
this input pin. Alternatively, tying this pin to V
external clock, the mark-space ratio can vary from 30/70 to 70/30.
Channel A/Channel B Select Input. Selects Channel A or Channel B of the DAC or ADC.
Used in conjunction with WR, RD, CS and ADC/DAC for read or write operations.
Digital Ground.
ADC or DAC Select Input. Selects either the ADC or the DAC for read or write operations in
conjunction with WR, RD, CS and CHA/CHB.
Write Input (edge triggered). This is used in conjunction with the ADC/DAC, CHA/CHB and CS
control inputs to start an ADC conversion or write data to the DAC. An ADC conversion starts on the
rising edge of WR.
Read Input (active low). This input must be low to access data from the ADC.
Chip Select Input (active low). The device is selected when this input is low.
ADC Reference Input. The voltage applied to this pin with respect to AGND (ADC) sets the
in put voltage Full-Scale Range (FSR) of the ADC. V
ADC Analog Ground.
Analog Input for Channel B. See V
ADC Reference Input. The voltage applied to this pin with respect to AGND (ADC) sets the
midpoint of the ADC transfer function.
Analog Input for Channel A. The input voltage range of both ADC channels is given by:
V
DAC Analog Ground.
DAC Reference Input. The voltage applied to this pin with respect to AGND (DAC) sets the
output voltage Full-Scale Range (FSR) of the DACs. V
Analog Output Voltage from DAC B. See V
DAC Reference Input. The voltage applied to this pin with respect to AGND (DAC) sets the
midpoint output voltage of the DACs.
Analog Output Voltage from DAC A. The output voltage range of both DACs is given by:
V
IN
OUT
A/B = V
A/B = V
BIAS
BIAS
(ADC) V
(DAC)
SWING
V
SWING
(ADC).
–6–
IN
(DAC).
A description.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB max en-
sures monotonicity (DAC) or no missed codes (ADC).
Bias Offset Error
For an ideal ADC, the output code for an input voltage equal to
V
Bias Offset Error is the difference between the actual midpoint
voltage for code 80 Hex and V
For an ideal DAC, the output voltage for code 80 Hex should
be equal to V
difference between the actual output voltage and V
expressed in LSBs.
BIAS
OUT
(ADC), should be 80 Hex (10000000 binary). The ADC
DD
A description.
enables the internal clock oscillator. With an
BIAS
IN
OUT
(FSR) = 2 V
(DAC). The DAC Bias Offset Error is the
(FSR) = 2 V
SWING
BIAS
SWING
(ADC), expressed in LSBs.
(ADC).
(DAC).
BIAS
(DAC),
REV. A