NHIXP435AE Intel, NHIXP435AE Datasheet - Page 11

• Manufacturer Part Number: NHIXP435AE
• Manufacturer: Intel

Specifications of NHIXP435AE

• Core Operating Frequency: 667MHz
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

4.0 Non-Intel XScale
4.0
1.
Problem:
Implication:
Workaround:
Status:
2.
Problem:
Implication:
Workaround:
Status:
3.
Problem:
Implication:
Workaround:
Status:
4.
Problem:
Implication:
Workaround:
Status:
December 2008
Order Number: 316847; Revision:
Non-Intel XScale
HDLC Coprocessor Is Unable to Capture the Alignment Error on a
Specific Frame Pattern
Based on ITU-T Q.921, during transmission, a bit stuffing ‘0’ is inserted after five
consecutive ‘1’ bits (including the FCS field) and then removed at the receiving end.
The bit stuffing ensures that the data does not appear as the ‘end of frame’ flag
(01111110). If five ‘1’s are received without a bit stuffing ‘0’, a ‘byte alignment error’
will be issued. The HDLC controller of the IXP43X product line of network processors
will not issue a ‘byte alignment error’ when the following boundary condition occurs:
An HDLC frame received by the IXP43X product line of network processors HDLC
controller from a Q.921 compliant HDLC controller with the same pattern described
above will not generate a ‘byte alignment error’; an FCS error will be issued by the
HDLC controller.
None
No Fix.
PCI Accesses to the Queue Manager During Queue and SRAM Mode
Under certain data traffic, the PCI controller may generate spurious write transfers and
may return incorrect data on reads while accessing the Queue Manager in SRAM mode.
Additionally, if the Queue Manager is being used in the Queue mode, PCI accesses must
not use memory-mapped registers BAR0-3 as these accesses cause pre-fetches during
reads.
Pre-fetches will cause loss of queue data.
Do not use the Queue Manager's SRAM mode during PCI accesses. Instead use the
DDRII/DDRI SDRAM memory space while generating PCI accesses to the memory
space of the IXP43X network processors. An external PCI master must use PCI BAR5
while accessing the Queue Manager in Queue mode.
No Fix.
Ethernet Control Protocol Frames Transmit-Defer Status Bit Error
Ethernet control protocol transmit frames of size 64 or less result in the Transmit-Defer
status bit being set regardless of the gap between the frames.
The Transmit-Defer Status bit in the IXP43X network processors is unusable.
None.
No Fix.
PCI Doorbell Register Lock-up Condition When Using Two Products
Together that have Intel
It is possible that the PCI bus can get in a locked condition when multiple products
using the IXP4XX product line processors are connected in a system and these systems
are using the PCI doorbell registers of the IXP4XX product line processors. This lockup
occurs only when both the IXP4XX product line processors attempt to access each
other’s PCI doorbell register at a particular instance. This error occurs only on reads of
the of the doorbell register.
When using two products that use the IXP4XX product line processors and their PCI
doorbell registers, PCI doorbell register reads cannot be implemented.
Perform doorbell register write from PCI bus to generate interrupt, and use regular
memory to pass information.
No Fix.
1. The receiving frame ends with five ‘1’s (FCS) followed by an ‘end of frame’ flag:
2. The ‘end of frame’ flag received is byte aligned.
“xx011111 01111110”
AND
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Technology Errata Descriptions
005US
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IXP4XX Product Line of Network Processors
Technology Errata Descriptions
Intel
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IXP43X Product Line of Network Processors
Specification Update
11