EWIXP425BBT Intel, EWIXP425BBT Datasheet - Page 47
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
EWIXP425BBT
Manufacturer Part Number
EWIXP425BBT
Description
Manufacturer
Intel
Datasheet
1.EWIXP425BBT.pdf
(130 pages)
Specifications of EWIXP425BBT
Core Operating Frequency
266MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
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Intel
Table 18.
Table 19.
August 2006
Document Number: 252479-006US
®
IXP42X product line and IXC1100 control plane processors
JTAG Interface (Sheet 2 of 2)
System Interface
†
BYPASS_CLK
SCANTESTMODE_N
RESET_IN_N
PWRON_RESET_N
HIGHZ_N
PLL_LOCK
RCOMP
†
††
JTG_TRST_N
JTG_TDO
JTG_TCK
Name
Name
For a legend of the Type codes, see
For a legend of the Type codes, see
IMPORTANT NOTE: When a system-level reset is asserted to the Intel
Network Processors and IXC1100 Control Plane Processor — either via a power-on reset, a system
reset, or a Watchdog-Timer reset — and any interface is in an active transaction (particularly the PCI
bus or expansion bus, but not precluding any interface), an illegal protocol is generated. The behavior
of the IXP42X product line and IXC1100 control plane processors is undefined in this situation and a
reset of other attached devices may be required.
Power
or Sys
Reset
Reset
Z
H
Z
Intel
††
Tied off
resistor
Power
or Sys
Reset
Reset
to a
®
Reset
H
H
Z
0
0
0
VI/PE
Post
VO
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
VI
Tied off
resistor
Reset
VI/PE
VI/PE
Post
Type
to a
VO
VI
VI
VI
O
I
I
†
Type
Table 5 on page
Table 5 on page
Output data for the IEEE 1149.1 JTAG interface.
Used to reset the IEEE 1149.1 JTAG interface.
The JTG_TRST_N signal must be asserted (driven low) during
power-up, otherwise the TAP controller may not be initialized
properly, and the processor may be locked.
When the JTAG interface is not being used, the signal must be
pulled low using a 10-KΩ resistor.
Used as the clock for the IEEE 1149.1 JTAG interface.
O
O
I
I
I
I
I
†
Used for test purposes only.
Must be pulled high for normal operation.
Used for test purposes only.
Must be pulled high for normal operation.
Used as a reset input to the device when
PWRON_RESET_N is in an inactive state and once power
up conditions are met. Power up conditions include the
following:
Signal used at power up to reset all internal logic to a
known state after the PLL has achieved a locked state.
The PWRON_RESET_N input is a 1.3-V tolerant only.
Used for test purposes only.
Must be pulled high for normal operation.
Signal used to inform external reset logic that the
internal PLL has achieved a locked state.
Signal used to control PCI drive strength characteristics.
Drive strength is varied on PCI address, data and control
signals.
Pin requires a 34-Ω +/- 1% tolerance resistor to ground.
Refer to
— Power supplies reaching a safe stable
— The PLL achieving a locked state
33.
33.
Figure 13 on page
condition and
Description
Description
®
82.
IXP42X Product Line of
Datasheet
47
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