PEF80912HV14NP Lantiq, PEF80912HV14NP Datasheet - Page 16

• Manufacturer Part Number: PEF80912HV14NP
• Manufacturer: Lantiq

Specifications of PEF80912HV14NP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 2
Pin
7
16
17
18
5
6
10
13
14
15
Data Sheet
Pin Definitions and Functions (cont’d)
Symbol
DIO
AUA
CSO
BUS
RST
RSTO
TLL
TM0
TM1
TM2
Type
I
I
I
I
(PU)
I
OD
I
I
I
I
Function
Disable IOM
1: FSC, DCL, DU and DD high Z
0: FSC, DCL, DU and DD push-pull
Auto U Activation:
1: U-transceiver attempts one automatic
activation after reset. Tie to ’0’ in applications
that do not require auto-start after reset.
Cold Start Only:
’1’ selects CSO-bit to ’0’. (normal)
’0’ selects CSO-bit to ’1’. (special cases)
The pin only controls the CSO-bit in the U-
frame. The U-transceiver itself is always a
warm-start transceiver according to ANSI and
ETSI.
Bus mode on S-interface:
1: passive S-bus (fixed timing)
0: point-to-point / extended passive S-bus
(adaptive timing)
Reset:
Low active reset input. Schmitt-Trigger input
with hysteresis of typical 360 mV. Tie to ’1’ if not
used.
Reset Output:
Low active reset output.
Triple-Last-Look
Select validation algorithm for received M4 bit
towards state machine:
’0’: CRC & TLL
’1’: CRC
Test Mode 0
Selects test pattern (see
Test Mode 1
Selects test pattern (see
Test Mode 2
Selects test pattern (see
8
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PEF 80912/80913
11).
11).
11).
2001-03-29
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