PEF80902HV11XP Lantiq, PEF80902HV11XP Datasheet - Page 21

• Manufacturer Part Number: PEF80902HV11XP
• Manufacturer: Lantiq

Specifications of PEF80902HV11XP

• Lead Free Status / Rohs Status: Compliant

2
2.1
External Reset Input
At the RST input an external reset can be applied forcing the T-SMINT
state. This external reset signal is additionally fed to the RSTO output.
Reset Ouput
If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by
t
Reset Generation
The T-SMINT
Under Voltage Detection (UVD) circuit (see
external components.
The POR/UVD circuit can be disabled via pin VDDDET.
The requirements on V
Chapter
Clocks and Data Lines During Reset
During reset the data clock (DCL) and the frame synchronization (FSC) keep running.
During reset DD and DU are high; with the exception of:
• The output C/I code from the U-Transceiver on DD is ’DR’ = 0000
• The output C/I code from the S-Transceiver on DU is ’TIM’ = 0000.
Data Sheet
DEACT
(see
4.6.3.
Functional Description
Reset Generation
Table
â
O has an on-chip reset generator based on a Power-On Reset (POR) and
28).
DD
ramp-up during power-on reset are described in
13
Table
28). The POR/UVD requires no
Functional Description
â
O in the reset
PEF 80902
2001-11-12