AD8317-EVALZ Analog Devices Inc, AD8317-EVALZ Datasheet - Page 11

• Manufacturer Part Number: AD8317-EVALZ
• Manufacturer: Analog Devices Inc

Specifications of AD8317-EVALZ

• Lead Free Status / Rohs Status: Compliant

USING THE AD8317
BASIC CONNECTIONS
The AD8317 is specified for operation up to 10 GHz; as a result,
low impedance supply pins with adequate isolation between
functions are essential. A power supply voltage of between 3.0 V
and 5.5 V should be applied to VPOS. Power supply decoupling
capacitors of 100 pF and 0.1 μF should be connected close to
this power supply pin.
The paddle of the LFCSP package is internally connected to
COMM. For optimum thermal and electrical performance, the
paddle should be soldered to a low impedance ground plane.
INPUT SIGNAL COUPLING
The RF input (INHI) is single-ended and must be ac-coupled.
INLO (input common) should be ac-coupled to ground.
Suggested coupling capacitors are 47 nF ceramic 0402-style
capacitors for input frequencies of 1 MHz to 10 GHz. The
coupling capacitors should be mounted close to the INHI and
INLO pins. The coupling capacitor values can be increased to
lower the high-pass cutoff frequency of the input stage. The
high-pass corner is set by the input coupling capacitors and the
internal 10 pF high-pass capacitor. The dc voltage on INHI and
INLO is approximately one diode voltage drop below V
While the input can be reactively matched, in general, this is not
necessary. An external 52.3 Ω shunt resistor (connected on the
signal side of the input coupling capacitors, as shown in
1
2
SIGNAL
SEE THE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE SECTION.
SEE THE OUTPUT FILTERING SECTION.
INPUT
52.3Ω
VPOS
INLO
INHI
R1
18.7kΩ
5pF
47nF
47nF
C2
C1
Figure 22. Basic Connections
Figure 23. Input Interface
18.7kΩ
INLO
INHI
5pF
8
1
0.1µF
100pF
C5
C4
CURRENT
COMM
STAGE
VPOS
gm
AD8317
V
7
2
S
0Ω
R2
(3.0V TO 5.5V)
2kΩ
TADJ
CLPF
6
3
1
2
A = 9dB
VSET
VOUT
5
4
STAGE
FIRST
OFFSET
COMP
GAIN
R4
0Ω
POS
.
V
OUT
Rev. B | Page 11 of 20
Figure 22) combines with the relatively high input impedance to
give an adequate broadband 50 Ω match.
The coupling time constant, 50 × C
corner with a 3 dB attenuation at f
C1 = C2 = C
corner is ~68 kHz. In high frequency applications, f
as large as possible to minimize the coupling of unwanted low
frequency signals. In low frequency applications, a simple RC
network forming a low-pass filter should be added at the input
for similar reasons. This low-pass filter network should generally
be placed at the generator side of the coupling capacitors, thereby
lowering the required capacitance value for a given high-pass
corner frequency.
OUTPUT INTERFACE
The VOUT pin is driven by a PNP output stage. An internal
10 Ω resistor is placed in series with the output and the VOUT
pin. The rise time of the output is limited mainly by the slew
on CLPF. The fall time is an RC-limited slew given by the load
capacitance and the pull-down resistance at VOUT. There is an
internal pull-down resistor of 1.6 kΩ. A resistive load at VOUT
is placed in parallel with the internal pull-down resistor to
provide additional discharge current.
To reduce the fall time, VOUT should be loaded with a resistive
load of <1.6 kΩ. For example, with an external load of 150 Ω,
the AD8317 fall time is <7 ns.
SETPOINT INTERFACE
The V
internal op amp. The V
1.5 kΩ resistor to generate I
applied to VSET, the feedback loop forces
If V
The result is
SET
−I
V
SET
OUT
= V
D
× log
input drives the high impedance (40 kΩ) input of an
= (−I
OUT
COMM
C
VPOS
CLPF
. Using the typical value of 47 nF, this high-pass
VSET
/2x, then I
10
(V
D
× 1.5 kΩ × 2x) × log
IN
/V
0.8V
Figure 24. Output Interface
+
–
INTERCEPT
Figure 25. VSET Interface
20kΩ
SET
SET
20kΩ
voltage appears across the internal
= V
COMM
SET
V
) = I
SET
. When a portion of V
OUT
SET
/(2x × 1.5 kΩ).
HP
C
/2, forms a high-pass
= 1/(2π × 50 × C
10
(V
1.5kΩ
1200Ω
400Ω
IN
10Ω
COMM
/V
INTERCEPT
I
SET
VOUT
HP
AD8317
OUT
)
C
should be
), where
is
(2)