K4H561638J-LCCC000 Samsung Semiconductor, K4H561638J-LCCC000 Datasheet - Page 4

• Manufacturer Part Number: K4H561638J-LCCC000
• Manufacturer: Samsung Semiconductor
• Type: DDR SDRAMr

Specifications of K4H561638J-LCCC000

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 650ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 180mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Note
1. "-B3"(DDR333, CL=2.5) can support "-B0"(DDR266, CL=2.5)/ "-A2"(DDR266, CL=2).
2. “L” of Part number(12th digit) stands for RoHS compliant and Halogen-Free product.
K4H560438J
K4H560838J
K4H561638J
1.0 Key Features
2.0 Ordering Information
3.0 Operating Frequencies
K4H560438J-LC/LB3
K4H560438J-LC/LB0
K4H560838J-LC/LCC
K4H560838J-LC/LB3
K4H561638J-LC/LCC
K4H561638J-LC/LB3
• V
• V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II
•
RoHS compliant
DD
DD
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
Speed @CL2.5
Speed @CL2
Speed @CL3
CL-tRCD-tRP
: 2.5V ± 0.2V, V
: 2.6V ± 0.1V, V
Part No.
Lead-Free & Halogen-Free
DDQ
DDQ
: 2.5V ± 0.2V for DDR266, 333
: 2.6V ± 0.1V for DDR400
CC(DDR400@CL=3)
16M x 16
64M x 4
32M x 8
166MHz
200MHz
Org.
3-3-3
-
package
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Max Freq.
B3(DDR333@CL=2.5)
133MHz
166MHz
2.5-3-3
4 of 24
-
Interface
SSTL2
SSTL2
SSTL2
A2(DDR266@CL=2.0)
133MHz
133MHz
2-3-3
Lead-Free & Halogen-Free
Lead-Free & Halogen-Free
Lead-Free & Halogen-Free
-
66pin TSOP II
66pin TSOP II
66pin TSOP II
Package
Rev. 1.12 August 2008
B0(DDR266@CL=2.5)
DDR SDRAM
100MHz
133MHz
2.5-3-3
-
Note
1, 2
1, 2
1, 2
2
2
2