MT48LC8M32B2TG-6 Micron Technology Inc, MT48LC8M32B2TG-6 Datasheet - Page 30

MT48LC8M32B2TG-6

Manufacturer Part Number
MT48LC8M32B2TG-6
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC8M32B2TG-6

Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
165mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
10. READs or WRITEs listed under Command (Action) include READs or WRITEs with auto precharge enabled and READs or
11. Does not affect the state of the bank and acts as a NOP to that bank.
09005aef8140ad6d
MT48LC8M32B2_2.fm - Rev. B 10/04 EN
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
be applied on each positive clock edge during these states.
WRITEs with auto precharge disabled.
Refreshing:
Accessing mode
register:
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
Starts with registration of an AUTO REFRESH command and ends when
Once
Starts with registration of a LOAD MODE REGISTER command and ends when
has been met. Once
Once
t
t
RC is met, the SDRAM will be in the all banks idle state.
RP is met, all banks will be in the idle state.
t
MRD is met, the SDRAM will be in the all banks idle state.
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256Mb: x32
t
t
RC is met.
RP is met.
SDRAM
t
MRD

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