L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 70

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

Gigabit Ethernet Transceiver
Timing Specifications
Internal Delay
Table 69. RGMII 1000Base-T Transmit Timing
1. The PHY uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2.0 ns.
2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty cycle is not
70
violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.
Symbol
TsetupT
TsetupR
Duty_G
Duty_T
TholdT
TholdR
Tr/Tf
AT TRANSMITTER
Tcyc
GTX_CLK (TXC)
(at transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_EN
(TX_CTL)
GTX_CLK (TXC)
(at receiver)
TXC
AT TRANSMITTER
TXC
AT RECEIVER
AT RECEIVER
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
TX_CLK
TX_CTL
Data to Clock Output Setup (at transmitter—integrated
Clock to Data Output Hold (at transmitter—integrated delay)
Data to Clock Input Setup (at receiver—integrated delay)
Data to Clock Input Hold (at receiver—integrated delay)
Clock Cycle Duration
Duty Cycle for Gigabit
Duty Cycle for 10Base-T/100Base-TX
Rise/Fall Time (20%—80%)
delay)
Figure 18. RGMII 1000Base-T Transmit Timing—Internal Delay
1
(continued)
TXD[3:0]
TXD[3:0]
TXD[4]
TXEN
TX_EN
TXD[4]
2
3
Parameter
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[8:5]
TXD[7:4]
TX_ER
TXD[9]
3
TsetupT
TsetupR
TSKEWT
1
1
1
Min
1.2
1.2
1.0
1.0
7.2
45
40
—
Typ
TholdT
TholdR
2.0
2.0
2.0
2.0
—
50
50
8
TSKEWR
September 2007
TXC WITH
INTERNAL
DELAY
ADDED
Max
0.75
LSI Corporation
8.8
TXC with
internal
delay
added
—
—
—
—
55
60
Unit
ns
ns
ns
ns
ns
ns
%
%