21143TD Intel, 21143TD Datasheet - Page 7

• Manufacturer Part Number: 21143TD
• Manufacturer: Intel

Specifications of 21143TD

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

1.2
Preliminary
1. Carrier-sense multiple access with collision detection.
2. Media access control.
Datasheet
Microarchitecture
The following list describes the 21143 hardware components, and
of the 21143:
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PCI/CardBus interface—Includes all interface functions to the PCI and CardBus bus; handles
all interconnect control signals; and executes DMA and I/O transactions
Boot ROM port—Provides an interface to perform read and write operations to the boot ROM;
supports accesses to bytes or longwords (32-bit); and provides the ability to connect an
external 8-bit register to the boot ROM port
Serial ROM port—Provides a direct interface to a MicroWire ROM for storage of the Ethernet
address and system parameters
General-purpose register—Enables software use for input or output functions and LEDs
DMA—Contains independent receive and transmit controllers; handles data transfers between
CPU memory and onchip memory
FIFOs—Contains independent FIFOs for receive and transmit; supports automatic packet
deletion on receive (runt packets or after a collision) and packet retransmission after a collision
on transmit
TxM—Handles all CSMA/CD
FIFO to the ENDEC for transmission
RxM—Handles all CSMA/CD MAC receive operations, and transfers the network data from
the ENDEC to the receive FIFO
SIA interface—Performs 10-Mb/s physical layer network operations; implements the AUI and
10BASE-T functions, including the Manchester encoder and decoder functions
NWAY—Implements the IEEE 802.3 Auto-Negotiation algorithm
Physical coding sublayer—Implements the encoding and decoding sublayer of the
100BASE-TX (CAT5) specification, including the squelch feature
Scrambler/descrambler—Implements the twisted-pair physical layer medium dependent
(TP-PMD) scrambler/descrambler scheme for 100BASE-TX
Three network interfaces—An AUI interface, a 10BASE-T interface, and an MII/SYM
interface provide a full MII signal interface and direct interface to the 100-Mb/s ENDEC for
CAT5
Wake-up-controller—Enables power-management control compliant with the ACPI and
remote power-up capabilities using the remote wake-up-LAN mechanism
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MAC
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transmit operations, and transfers data from transmit
Figure 1
shows a block diagram
21143
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