RG82865GV S L77X Intel, RG82865GV S L77X Datasheet
RG82865GV S L77X
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RG82865GV S L77X Summary of contents
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... Intel 865G/865GV Chipset Datasheet ® Intel 82865G/82865GV Graphics and Memory Controller Hub (GMCH) February 2004 Document Number: 252514-005 ...
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... C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corpora- tion. Intel, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other coun- tries. *Other names and brands may be claimed as the property of others. ...
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... Chipset System Overview ..........................................................18 ® 82865G GMCH Overview ....................................................................20 Host Interface....................................................................................20 System Memory Interface .................................................................20 Hub Interface ....................................................................................21 Communications Streaming Architecture (CSA) Interface ................21 Multiplexed AGP and Intel Graphics Overview............................................................................22 Display Interface ...............................................................................24 ..............................................................................................25 DDR SDRAM Channel A ..................................................................30 DDR SDRAM Channel B ..................................................................31 AGP Addressing Signals...................................................................33 AGP Flow Control Signals ................................................................34 AGP Status Signals ...
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... VID1—Vendor Identification Register (Device 1).............................. 88 DID1—Device Identification Register (Device 1) .............................. 88 PCICMD1—PCI Command Register (Device 1)............................... 89 PCISTS1—PCI Status Register (Device 1) ...................................... 90 RID1—Revision Identification Register (Device 1) ........................... 91 ® Intel 82865G/82865GV GMCH Datasheet ...
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... PMCAP—Power Management Capabilities Register 3.7.23 PMCS—Power Management Control/Status Register 3.7.24 SWSMI—Software SMI Interface Register (Device 2) ....................112 ® Intel 82865G/82865GV GMCH Datasheet SUBC1—Sub-Class Code Register (Device 1) ................................91 BCC1—Base Class Code Register (Device 1) .................................91 MLT1—Master Latency Timer Register (Device 1)...........................92 HDR1— ...
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... SUBC6—Sub-Class Code Register (Device 6) .............................. 130 BCC6—Base Class Code Register (Device 6) ............................... 130 HDR6—Header Type Register (Device 6) ...................................... 130 BAR6—Memory Delays Base Address Register (Device 6)........... 131 (Device 6) ....................................................................................... 131 (Device 6, MMR) ............................................................................. 132 ...................................................................................... 139 15 MB–16 MB Window ................................................................... 143 Pre-Allocated Memory .................................................................... 144 ® Intel 82865G/82865GV GMCH Datasheet ...
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... Raster Engine..................................................................168 2D Engine .......................................................................................172 Video Engine...................................................................................173 Planes .............................................................................................173 5.4.4.1 Cursor Plane....................................................................173 5.4.4.2 Overlay Plane ..................................................................174 Pipes ...............................................................................................175 Analog Display Port Characteristics................................................176 Digital Display Interface ..................................................................177 5.5.2.1 Digital Display Channels – Intel 177 ® ® DVOB and Intel DVOC ... 7 ...
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... Synchronous Display Differences ................................................................ 226 ® 10 Intel 82865GV GMCH Ballout ® 11 Intel 82865GV GMCH Testability 11.1 XOR Test Mode Initialization ....................................................................... 241 11.2 XOR Chain Definition................................................................................... 243 8 Synchronous Display ...................................................................... 180 Supported ACPI States................................................................... 180 External Thermal Sensor Interface Overview ................................. 181 5 ...
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... Figures 1 Intel 2 Intel 3 Intel 4 Full and Warm Reset Waveforms ..................................................................46 5 Conceptual Intel 6 Configuration Mechanism Type 0 Configuration Address-to-PCI Address Mapping .................................................................51 7 Configuration Mechanism Type 1 Configuration Address-to-PCI Address Mapping .................................................................52 8 PAM Register Attributes.................................................................................70 9 Memory System Address Map.....................................................................140 10 Detailed Memory System Address Map......................................................140 11 Single-Channel Mode Operation ...
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... Supported DDR DIMM Configurations......................................................... 156 26 Data Bytes on DIMM Used for Programming DRAM Registers................... 157 27 AGP Support Matrix..................................................................................... 159 28 AGP 3.0 Downshift Mode Parameters......................................................... 160 29 Pin and Strap Values Selecting Intel 30 AGP 3.0 Commands Compared to AGP 2.0 ............................................... 162 31 Supported Data Rates ................................................................................. 162 32 Display Port Characteristics......................................................................... 176 33 Analog Port Characteristics ...
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... XOR Chain 7 (45 Inputs) Output Pins: SDM_A7, SDM_B7 .........................248 65 XOR Chain 8 (40 Inputs) Output Pins: HTRDY#, BPRI# .............................248 66 XOR Chain 9 (62 Inputs) Output Pins: RS2#, DEFER#...............................249 67 XOR Excluded Pins .....................................................................................250 ® Intel 82865G/82865GV GMCH Datasheet ® 82865GV Ball List by Signal Name ....................................................231 11 ...
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... Section 3.5. • Corrected bit A1 in Table 24, RAM Address Translation, 512mb, 64Mx8, from bit 15 to 16. • Added 82865GV information • Replaced Figure 19 in Section 7.2 May 2003 June 2003 June 2003 September 2003 February 2004 ® Intel 82865G/82865GV GMCH Datasheet Date ...
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... Supports SSTL_2 signaling Communication Streaming Architecture (CSA) Interface I — Gigabit Ethernet (GbE) communication devices supported on ® the CSA interface (e.g., Intel 82547EI GbE controller) — Supports 8-bit Hub Interface 1.5 electrical/transfer protocol — 266 MB/s point-to-point connection — 1.5 V operation Hub Interface (HI) I — ...
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... This page is intentionally left blank. ® Intel 82865G/82865GV GMCH Datasheet ...
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... Intel Pentium package or the Intel 400 MHz, 533 MHz, and 800 MHz. The 82865G GMCH is part of the Intel 82865GV GMCH is part of the Intel components: Graphics and Memory Controller Hub (GMCH) for the host bridge and I/O Controller Hub for the I/O subsystem. The GMCH provides the processor interface, system memory interface, hub interface, CSA interface and other additional interfaces in an 865G/ 865GV chipset desktop platform ...
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... Graphics and Memory Controller Hub. The GMCH component contains the processor interface, SDRAM controller, AGP interface, CSA interface and an integrated 3D/2D/display GMCH graphics core. It communicates with the I/O controller hub (Intel interconnect called HI. Graphics Translation Look-aside Buffer. A cache used to store frequently used GART GTLB entries ...
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... Chipset CRB Schematics Addendum for ® ® the Intel Pentium 4 processor Process w/Loadline A Platforms - 3 Phase VR ® Intel 82801EB I/O Controller Hub 5 (ICH5) and Intel Controller Hub 5R (ICH5R) Datasheet ® ® Intel Pentium 4 processor with 512-KB L2 Cache on 0.13 Micron Process Datasheet ® ...
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... AGP. The IGD has 3D, 2D, and video capabilities. The IGD also has two multiplexed Intel DVO ports to support DVO devices. The GMCH’s AGP interface supports 1X/4X/8X AGP data transfers and 4X/8X AGP Fast Writes, as defined in the Accelerated Graphics Port Interface Specification, Revision 3 ...
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... Figure 1. Intel 865G Chipset System Block Diagram VGA AGP 8x/ 2 multiplexed DVO ports CSA Interface Gigabit Ethernet USB 2.0 8 ports, 480 Mb/s GPIO 2 Serial ATA Ports 150 MB/s 2 ATA 100 Ports AC '97 3 CODEC support ® Intel 82865G/82865GV GMCH Datasheet Processor ...
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... Supports opportunistic refresh • simultaneously open pages (four per row, four rows maximum) • SPD (Serial Presence Detect) scheme for DIMM detection support • Suspend-to-RAM support using CKE • Supports configurations defined in the JEDEC DDR1 DIMM specification only 20 ® Intel 82865G/82865GV GMCH Datasheet ...
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... The CSA interface runs at 266 MT/s (with 66 MHz base clock) and uses 1.5 V signaling. 1.4.5 Multiplexed AGP and Intel The GMCH multiplexes an AGP interface with two Intel AGP Interface A single AGP or PCI 66 component or connector (not both) is supported by the GMCH’s AGP interface ...
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... ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination. Performing these common tasks in hardware reduces processor load, and thus improves performance. The internal graphics device incorporated in the GMCH is incapable of operating in parallel with an attached AGP device. 22 ® Intel 82865G/82865GV GMCH Datasheet ...
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... Alpha Blended Cursor — Color Space Conversion — Programmable 3-Color Transparent Cursor — 8-, 16- and 32-bit Color — ROP Support ® Intel 82865G/82865GV GMCH Datasheet Introduction • 3D Graphics Rendering Enhancements — Flat and Gouraud Shading — Color Alpha Blending For Transparency — ...
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... MT/s DDR-DRAM 1/1 266 MT/s DDR-DRAM 3/2 266 MT/s DDR-DRAM 4/5 333 MT/s DDR-DRAM 5/4 320 MT/s DDR-DRAM 1/1 400 MT/s DDR-DRAM ® Intel 82865G/82865GV GMCH Datasheet Peak Bandwidth 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.7 GB/s 2.6 GB/s 3.2 GB/s ...
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... All processor control signals follow normal convention (zero) indicates an active low level (low voltage) if the signal name is followed by # symbol (one) indicates an active high level (high voltage) if the signal has no # suffix. ® Intel 82865G/82865GV GMCH Datasheet Input pin Output pin Bi-directional Input/Output pin Sustained Tri-state ...
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... Signal Description ® Figure 2. Intel 82865G GMCH Interface Block Diagram HA[31:3]# HD[63:0]# HREQ[4:0]# CPURST# DINV[3:0]# HADSTB[1:0]# HDSTBP[3:0]#, HDSTBN[3:0]# SCS_A[3:0]# SMAA_A[12:0], SMAB_A[5:1] SBA_A[1:0] SRAS_A# SCAS_A# SDQ_A[63:0] SDM_A[7:0] SDQS_A[8:0] SCKE_A[3:0] SCMDCLK_A[5:0], SCMDCLK_A[5:0]# SCS_B[3:0]# SMAA_B[12:0], SMAB_B[5:1] SBA_B[1:0] SRAS_B# SCAS_B# SDQ_B[63:0] SDM_B[7:0] SDQS_B[8:0] SCKE_B[3:0] SCMDCLK_B[5:0], SCMDCLK_B[5:0]# ...
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... HCLKs. BREQ0# O should be terminated high (pulled up) after the hold time requirement has been satisfied. NOTE: This signal is called BR0# in the Intel specifications. Core / FSB Frequency (FSBFREQ) Select Strap: This strap is latched at the rising edge of PWROK. These pins has no default internal pull-up resistor. ...
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... In the second half the signals carry additional information to define the complete transaction type. Description Data Bits HD[63:48]#, DINV3# HD[47:32]#, DINV2# HD[31:16]#, DINV1# HD[15:0]#, DINV0# ® Intel 82865G/82865GV GMCH Datasheet ...
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... Processor Internal Error BINIT# Bus Initialization Signal MCERR# Machine Check Error ® Intel 82865G/82865GV GMCH Datasheet O Host Target Ready: This signal indicates that the target of the processor transaction is able to enter the data transfer phase. I/0 Processor Hot: This signal informs the chipset when the processor Tj is greater than the thermal Monitor trip point ...
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... Clock Enable: SCKE_A[3:0] are used to initialize DDR SDRAM during power-up and to place all SDRAM rows into and out of self-refresh during O Suspend-to-RAM. SCKE_A[3:0] are also used to dynamically power SSTL_2 down inactive SDRAM rows. There is one SCKE_Ax per SDRAM row, toggled on the positive edge of SCMDCLK_Ax. Intel Description ® 82865G/82865GV GMCH Datasheet ...
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... SRAS_B# SCAS_B# SWE_B# SDQ_B[63:0] SDM_B[7:0] SDQS_B[7:0] SCKE_B[3:0] ® Intel 82865G/82865GV GMCH Datasheet Type Differential DDR Clock: SCMDCLK_Bx and SCMDCLK_Bx# are differential clock output pairs. The crossing of the positive edge of O SCMDCLK_Bx and the negative edge of SCMDCLK_Bx# is used to SSTL_2 sample the address and control signals on the SDRAM. There are three pairs to each DIMM ...
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... Packet Data: CI[10:0] are data signals used for CI read and write operations. Packet Strobe: CISTRS is one of two differential strobe signals used to transmit or receive packet data over CI. Packet Strobe Complement: CISTRF is one of two differential strobe signals used to transmit or receive packet data over CI. ® Intel 82865G/82865GV GMCH Datasheet ...
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... The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 3. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing). ® Intel 82865G/82865GV GMCH Datasheet Type Pipelined Read: This signal is asserted by the current master to indicate a full width address queued by the target ...
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... Reserved in AGP 3.0 signaling mode. 100 Reserved. 101 Reserved. 110 Reserved. 111 The master has been given permission to start a bus transaction. The master may queue AGP requests by asserting GPIPE# (4X signaling mode) or start a PCI transaction by asserting GFRAME(#). ® Intel 82865G/82865GV GMCH Datasheet ...
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... The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing). 2. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing). ® Intel 82865G/82865GV GMCH Datasheet Type AD Bus Strobe-0: GADSTB0 provides timing for 4X clocked data on GAD[15:0] and GC/BE[1:0]# in AGP 2 ...
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... I/O transactions and the data for all transactions. These signals operate AGP data rate for GFRAME(#) based cycles, and operate at the specified channel rate (1X, 4X, or 8X) for AGP data phases and fast write data phases. Intel Description ® 82865G/82865GV GMCH Datasheet ...
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... DVOB Clock Output: These pins provide a differential pair reference clock O that can run up to 165 MHz. Care should be taken to be sure that DVOB_CLK AGP is connected to the primary clock receiver of the Intel O DVOB Data: This data bus is used to drive 12-bit pixel data on each edge of AGP DVOB_CLK(#) ...
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... This signal is tri-stated during a hard AGP reset. ADD Card ID: These signals will be strapped on the ADD card for SW I/O identification purposes. These signals may need pull-up or pull-down resistors AGP in a DVO down scenario. Description ® Intel 82865G/82865GV GMCH Datasheet ...
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... ADD_ID. When an ADD card is present, ADD_DETECT = 0 (DVO mode), the ADD_ID register (offset 71408h) will hold a valid ADD PROM ID. Table 3 shows the DVO-to-AGP pin mapping. The AGP signal name column only shows the AGP 2.0 signal names. ® Table 3. Intel DVO-to-AGP Pin Mapping DVO Signal Name DVOB_D0 DVOB_D1 DVOB_D2 ...
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... NOTE: This signal may need to be level shifted to 5 Volts. Analog DDC Data: Data signal for the I I/O Analog CRT Display. NOTE: This signal may need to be level shifted to 5 Volts. Description 2 C style interface that connects style interface that connects to ® Intel 82865G/82865GV GMCH Datasheet ...
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... PWROK LVTTL EXTTS# LVTTL TESTIN# ® Intel 82865G/82865GV GMCH Datasheet Differential Host Clock In: These pins receive a low voltage differential host I clock from the external clock synthesizer. This clock is used by all of the GMCH logic that is in the Host clock domain 0 MHz Clock In:. This pin receives a 66 MHz clock from the clock synthesizer. ...
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... DVOBCRCOMP HI_VREF HI_RCOMP HI_SWING CI_VREF CI_RCOMP CI_SWING NOTE: 1. Reference the Intel information. 42 Type Host Data Reference Voltage: This signal is the reference voltage input for I the data signals of the Host AGTL+ interface. I/O Host RCOMP: HDRCOMP is used to calibrate the Host AGTL+ I/O buffers. ...
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... VCCA_DPLL Intel VCC_DAC DAC VCC Supply: This signal is the 3.3 V VCC for the DAC. Analog DAC VCC: This is the 1.5 V analog supply for the DAC. Refer to the Intel VCCA_DAC 865GV/865PE/865P Chipset Platform Design Guide for supply requirements. VSSA_DAC Analog DAC VSS: This supply should go directly to motherboard ground. ...
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... GCLKIN must be valid at least 10 µs prior to the rising edge of PWROK. • HCLKN/HCLKP must be valid at least 10 µs prior to the rising edge of RSTIN#. There is no DREFCLK timing requirements relative to reset. ® Figure 3. Intel 865G Chipset System Clock and Reset Requirements POWER PWROK RSTIN# ...
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... Signal Name Type I BSEL[1:0] CMOS ® Intel 82865G/82865GV GMCH Datasheet Strap Name System Bus IOQ Depth Strap: The value on HA7# is sampled by all processor bus agents, including the GMCH, on the deasserting edge of CPURST#. NOTE: For HA7#, the minimum setup time is 4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs ...
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... PCIRST# (GMCH RSTIN#) is asserted and PWROK is also asserted. The following table describes the reset states. Reset State Full Reset Warm Reset Does Not Occur Normal Operation Min 1 ms Unknown Full Reset Warm Reset RSTIN# PWROK Intel Write min CF9h 1 ms Running Warm Reset Running ® 82865G/82865GV GMCH Datasheet ...
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... That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note that software does not need to perform a read-merge-write operation for the Configuration Address (CONFIG_ADDRESS) register. ® Intel 82865G/82865GV GMCH Datasheet Register Description Description 3 ...
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... Reserved have no effect on the GMCH. Registers Caution: Register locations that are marked as “Intel Reserved” must not be modified Upon a reset, the GMCH sets all of its internal configuration registers to predetermined default states. Some register values at reset are determined by external strapping options. The default state represents the minimum functionality feature set required to Default Value successfully bring up the system ...
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... PCI 0 while the secondary side is the standard PCI expansion bus. Note: A physical PCI bus 0 does not exist; HI and the internal devices in the GMCH and ICH5 logically constitute PCI Bus 0 to configuration software. Figure 5. Conceptual Intel ® Intel 82865G/82865GV GMCH Datasheet Bus #0, Device # ® ...
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... If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the Host- AGP/PCI_B device’s Secondary Bus Number register or greater than the value in the Host-AGP/ PCI_B device’s Subordinate Bus Number register, the GMCH generates a Type 1 HI Configuration 50 ® Intel 82865G/82865GV GMCH Datasheet ...
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... Address-to-PCI Address Mapping 31 1 Reserved 31 Table 5. Configuration Address Decoding Config Addr AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 ® Intel 82865G/82865GV GMCH Datasheet Figure 7. This HI configuration cycle is sent over HI. Figure 6. CONFIG_ADDRESS Bus Number Device Number IDSEL Reserved = 0 AGP GAD[31:0] Address ...
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... The Configuration Address register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window Reserve Bus Device 1 Function Number d Number Number Bus Device 0 Function Number Number Number ® Intel Reg. Index Reg. Index 82865G/82865GV GMCH Datasheet ...
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... Configuration Address register. This field is mapped to GAD[7:2] during AGP/PCI_B Configuration cycles and A[7:2] during HI configuration cycles. 1:0 Reserved. These bits are read only. ® Intel 82865G/82865GV GMCH Datasheet 0CF8h–0CFBh (Accessed as a DWord) 00000000h R/W 32 bits ...
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... CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Bit Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, any I/O access to 31:0 CONFIG_DATA are mapped to configuration space using the contents of CONFIG_ADDRESS. 54 0CFCh–0CFFh 00000000h R/W 32 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
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... Header Type Intel Reserved Aperture Base Configuration Intel Reserved Subsystem Vendor Identification Subsystem Identification Intel Reserved Capabilities Pointer Intel Reserved AGP Miscellaneous Configuration Graphics Control CSA Basic Control Intel Reserved FPLL Clock Control Intel Reserved Programmable Attribute Map 0 Programmable Attribute Map 1 ...
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... Intel Reserved Aperture Translation Table AGP MTT Control AGP Low Priority Transaction Timer Intel Reserved Top of Used DRAM GMCH Configuration Error Status Error Command Intel Reserved Scratchpad Data Intel Reserved Capability Identification Intel Reserved ® Intel 82865G/82865GV GMCH Datasheet Default Value ...
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... The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identifies any PCI device. Bit Vendor Identification (VID)—RO. This register field contains the PCI standard identification for 15:0 Intel, 8086h. 3.5.2 DID—Device Identification Register (Device 0) Address Offset: Default Value: ...
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... Bus Master Enable (BME)—RO. Hardwired to 1. GMCH is always enabled as a master on HI. Memory Access Enable (MAE)—RO. Hardwired to 1. The GMCH always allows access to main 1 memory. 0 I/O Access Enable (IOAE)—RO. Hardwired 04–05h 0006h RO, R/W 16 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
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... A list of new capabilities is accessed via 4 register CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the AGP Capability standard register resides. 3:0 Reserved. ® Intel 82865G/82865GV GMCH Datasheet 06–07h 0090h RO, R/WC 16 bits Descriptions Register Description ...
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... Base Class Code (BASEC)—RO. This is an 8-bit value that indicates the Base Class Code for the GMCH. 7:0 06h = Bridge device. 60 08h See table below RO 8 bits Descriptions 0Ah 00h RO 8 bits Descriptions 0Bh 06h RO 8 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
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... This register identifies the header layout of the configuration space. No physical register exists at this location. Bit PCI Header (HDR)—RO. This field always returns 0 to indicate that the GMCH is a single function 7:0 device with standard header layout. ® Intel 82865G/82865GV GMCH Datasheet 0Dh 00h RO 8 bits Descriptions ...
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... PCI specification for base address registers. Memory Space Indicator (MSPACE)—RO. Hardwired identify the aperture range memory range as per the specification for PCI base address registers. 62 10–13h 00000008h RO, R/W 32 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
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... Bit Capabilities Pointer Address— RO. This field contains the pointer to the offset of the first 7:0 capability ID register block. In this case the first capability is the Product-Specific Capability, which is located at offset E4h. ® Intel 82865G/82865GV GMCH Datasheet 2C–2Dh 0000h R/WO 16 bits Descriptions 2E– ...
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... SDRAM has been initialized Disable.The default value this field must be set after system is fully configured to enable aperture accesses Enable. 0 Reserved. 64 51h 00h R/W 8 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
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... IGD claims VGA memory and I/O cycles; the Sub-Class Code within Device 2 Class Code 1 register is 00h. (Default IGD does not claim VGA cycles (Memory and I/O); the Sub-Class Code field within Device 2 Class Code register is 80h. 0 Reserved ® Intel 82865G/82865GV GMCH Datasheet 52h 0000_1000h R/W, R/W/L 8 bits Descriptions Register Description ...
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... Range Destination VGA, MDA Hub Interface Illegal Illegal VGA, MDA AGP VGA, MDA AGP, Hub Interface Intel AND Device 2 in powered up D0 state B8000h–BFFFFh IGD PCI-to-PCI Bridge or Hub Interface PCI-to-PCI Bridge or Hub Interface IGD Exceptions/Notes Illegal ® ...
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... Address Offset: Default: Access: Size: Bit 7:1 Reserved. Device Not Present bit—R/ Device Not Enabled 1 = Device Enabled ® Intel 82865G/82865GV GMCH Datasheet 3CX 3DX PCI-to-PCI Bridge IGD or Hub Interface IGD IGD Range Destination x3BCh – x3BFh goes to AGP if ISA enabled bit is ...
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... Writing a 1 cleanly disables the graphics and memory clocks while still enabling the core 0 clocks. The memory and graphics clocks can then be programmed with new speed information. NOTE: This bit should always be written to before writing to the FPLLSYNC bit. 68 60h 00h R/ bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
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... the time that AGP access to the PAM region may occur, the targeted PAM segment must be programmed to be both readable and writable. ® Intel 82865G/82865GV GMCH Datasheet 90–96h (PAM0–PAM6) 00h R/ bits each register Bits [5, 1] Bits [ Disabled. Main memory is disabled and all accesses are directed to the Hub Interface A ...
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... ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS ISA Add-on BIOS BIOS Extension BIOS Extension BIOS Extension BIOS Extension ® Intel 82865G/82865GV GMCH Datasheet Offset 90h 90h 90h 91h 91h 92h 92h 93h 93h ...
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... Bit Hole Enable (HEN)—R/W. This field enables a memory hole in SDRAM space. The SDRAM that lies “behind” this space is not remapped =Disable. No memory hole. 1 =Enable. Memory hole from MB. 6:0 Reserved. ® Intel 82865G/82865GV GMCH Datasheet Table Table 7. Table 7. 97h 00h ...
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... SMM space. SMM SDRAM is not remapped simply made visible if the conditions are right 2:0 to access SMM space, otherwise the access is forwarded to HI. Since the GMCH supports only the SMM space between A0000h and BFFFFh, this field is hardwired to 010. 72 9Dh 02h R/W, RO, Lock 8 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
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... TSEG Enable (T_EN)—R/W/L. This bit enables SMRAM memory for Extended SMRAM space 0 only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Note that once D_LCK is set, this bit becomes read only. ® Intel 82865G/82865GV GMCH Datasheet 9Eh 38h R/W, R/WC, RO, Lock ...
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... Greater Than Four Gigabyte Support (GT4GIG)—RO. Hardwired to 0, indicating that the GMCH 5 does not support addresses greater than 4 GB. 74 A0h–A3h 00300002h RO 32 bits Descriptions A4–A7h 1F004217h in AGP 2.0 mode 1F004A13h in AGP 3.0 mode RO 32 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
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... In AGP 3.0 mode (AGP_MODE=1) these bits are 011 indicating that both 4X and 8X modes are supported AGP 2.0 mode these bits are 111 indicating that 4X, 2X, and 1X modes are supported; however, in the 82865G GMCH 2X is not supported. ® Intel 82865G/82865GV GMCH Datasheet Register Description Descriptions 75 ...
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... Transfer Mode (for AGP 2.0 signaling) AGP 3.0 001= 4X transfer mode (for AGP 3.0 signaling) 010= 8X Transfer mode (for AGP 3.0 signaling) 100= Reserved 76 A8–ABh 00000000h in AGP 2.0 mode 00000A00h in AGP 3.0 mode RO, R/W 32 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
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... Override (OVER4X)—R/W. This back-door register bit allows the BIOS to force 1X mode for AGP 2.0 and 4X mode for AGP 3.0. Note that this bit must be set by the BIOS before AGP configuration override 1 = The RATE[2:0] bit in the AGPSTS register will be read as a 001. ® Intel 82865G/82865GV GMCH Datasheet B0–B3h 00000000h RO, R/W 32 bits Descriptions ...
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... Note that it should be modified only when the GTLB has been disabled. 11:0 Reserved. 78 B4h 00h RO, R/W 8 bits Descriptions B8-BBh 00000000h RO, R/W 32 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
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... MHz clock granularity) allotted to the current agent 7:3 (either AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to another agent. 2:0 Reserved. ® Intel 82865G/82865GV GMCH Datasheet BCh 10h RO, R/W 8 bits Descriptions ...
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... Low Priority Transaction Timer Count Value (LPTTC)—R/W. The number of clocks 7:3 programmed in these bits represents the time slice (measured in eight 66 MHz clock granularity) allotted to the current low priority AGP transaction data transfer state. 2:0 Reserved. 80 BDh 10h RO, R/W 8 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 81
... TOUD should be programmed to BCB0_0000h. NOTE: Even if the OS does not need any PCI space, TOUD should never be programmed above FEC0_0000h. If TOUD is programmed above this, address ranges that are reserved will become accessible to applications. 2:0 Reserved. ® Intel 82865G/82865GV GMCH Datasheet C4–C5h 0400h RO, R/W 16 bits Descriptions ...
Page 82
... VGA references go to AGP/PCI; MDA references go to HI. System Memory DDR set to 266 MHz System Memory DDR set to 266 MHz System Memory DDR set to 333 MHz System Memory DDR set to 333 (320) MHz System Memory DDR set to 400 MHz ® Intel 82865G/82865GV GMCH Datasheet ...
Page 83
... Core Frequency is 100 MHz and the FSB frequency is 400 MHz 1 Core Frequency is 133 MHz and the FSB frequency is 533 MHz 10 = Core Frequency is 200 MHz and the FSB frequency is 800 MHz 11 = Reserved ® Intel 82865G/82865GV GMCH Datasheet Descriptions ADD_DETECT Strap Resulting AGP/DVO# 0 ...
Page 84
... Invalid translation table entry was returned in response to an AGP access to the graphics aperture. GMCH Detects Unsupported AGP Command—R/WC unsupported AGP Command received Bogus or unsupported command is received by the AGP target in the GMCH. 0 Reserved 84 C8–C9h 0000h R/WC 16 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 85
... AGP access to the graphics aperture. SERR on GMCH Detects Unsupported AGP Command—R/ =GMCH Detects Unsupported AGP command will not generate a SERR. 1 =GMCH generates a SERR when an unsupported AGP command is detected. 0 Reserved ® Intel 82865G/82865GV GMCH Datasheet CA–CBh 0000h RO, R/W 16 bits Descriptions Register Description ...
Page 86
... CAP_ID—RO. This field has the value 09h to identify the CAP_ID assigned by the PCI SIG for 7:0 Vendor Dependent CAP_PTR. 86 DE–DFh 0000h R/W 16 bits Descriptions E4h–E9h 00000106A009h RO 48 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 87
... MLIMIT1 24–25h PMBASE1 26–27h PMLIMIT1 28–3Dh 3Eh BCTRL1 3Fh 40h ERRCMD1 41–FFh ® Intel 82865G/82865GV GMCH Datasheet Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification — Reserved Sub-Class Code Base Class Code — Reserved Master Latency Timer Header Type — ...
Page 88
... The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identify any PCI device. Bit Vendor Identification Device 1 (VID1)—RO. This register field contains the PCI standard 15:0 identification for Intel, 8086h. 3.6.2 DID1—Device Identification Register (Device 1) Address Offset: Default Value: ...
Page 89
... MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers. IO Access Enable (IOAE)—R/ Disable. All of Device 1’s I/O space is disabled Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and IOLIMIT1 registers. ® Intel 82865G/82865GV GMCH Datasheet 04–05h 0000h RO, R/W 16 bits Descriptions ...
Page 90
... Fast Back-to-Back (FB2B)—RO. Hardwired to 1. The AGP/PCI_B interface always supports fast 7 back-to-back writes. 6 Reserved. 5 66/60 MHz capability (CAP66)—RO. Hardwired to 1. The AGP/PCI bus is 66 MHz capable. 4:0 Reserved. 90 06–07h 00A0h RO, R/WC 16 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 91
... This register contains the Base Class Code of the GMCH Device 1. Bit Base Class Code (BASEC)—RO. This is an 8-bit value that indicates the Base Class Code for the GMCH Device 1. 7:0 06h = Bridge device. ® Intel 82865G/82865GV GMCH Datasheet 08h See table below RO 8 bits Descriptions ...
Page 92
... Since Device internal device and its primary bus is always 0, these bits are read only and are hardwired 0Dh 00h RO, R/W 8 bits Descriptions 0Eh 01h RO 8 bits Descriptions 18h 00h RO 8 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 93
... This register control the bus tenure of the GMCH on AGP/PCI the same way Device 0 MLT controls the access to the PCI_A bus. Bit 7:3 Secondary MLT Counter Value (MLT)—R/W. Programmable, default = 0 (SMLT disabled) 2:0 Reserved. ® Intel 82865G/82865GV GMCH Datasheet 19h 00h R/W 8 bits Descriptions 1Ah ...
Page 94
... I/O Address Limit (IOLIMIT)—R/W. This field corresponds to A[15:12] of the I/O address limit of 7:4 Device 1. Devices between this upper limit and IOBASE1 will be passed to AGP/PCI_B. 3:0 Reserved. 94 1Ch F0h RO, R/W 8 bits Descriptions 1Dh 00h RO, R/W 8 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 95
... Fast Back-to-Back (FB2B)—RO. Hardwired to 1. GMCH as a target supports fast back-to-back 7 transactions on PCI_B/AGP. 6 Reserved. 66/60 MHz capability (CAP66)—RO. Hardwired indicate that the AGP/PCI_B bus is 5 capable of 66 MHz operation. 4:0 Reserved. ® Intel 82865G/82865GV GMCH Datasheet 1E–1Fh 02A0h RO, R/WC 16 bits Descriptions Register Description 95 ...
Page 96
... Bit Memory Address Base (MBASE)— R/W. This field corresponds to A[31:20] of the lower limit of 15:4 the memory range that will be passed by the Device 1 bridge to AGP/PCI_B. 3:0 Reserved. 96 20–21h FFF0h RO, R/W 16 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 97
... Memory Address Limit (MLIMIT)—R/W. This field corresponds to A[31:20] of the memory 15:4 address that corresponds to the upper limit of the range of memory accesses that will be passed by the Device 1 bridge to AGP/PCI_B. 3:0 Reserved. ® Intel 82865G/82865GV GMCH Datasheet 22–23h 0000h RO, R/W 16 bits Descriptions ...
Page 98
... Bit Prefetchable Memory Address Limit (PMLIMIT)—R/W. This field corresponds to A[31:20] of the 15:4 upper limit of the address range passed by bridge Device 1 across AGP/PCI_B. 3:0 Reserved. 98 24–25h FFF0h RO, R/W 16 bits Descriptions 26–27h 0000h RO, R/W 16 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 99
... MDAP ® Intel 82865G/82865GV GMCH Datasheet 3Eh 00h RO, R/W 8 bits Descriptions All References to MDA and VGA space are routed to HI. Illegal combination. All VGA references are routed to this bus. MDA references are routed to HI. All VGA references are routed to this bus. MDA references are routed to HI. ...
Page 100
... GMCH does not assert a SERR message upon receipt of a target abort on PCI_B. SERR 0 messaging for Device 1 is globally enabled in the PCICMD1 register. 1 =The GMCH generates a SERR message over HI upon receiving a target abort on PCI_B. 100 40h 00h RO, R/W 8 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 101
... Video BIOS ROM Base Address Capabilities Pointer Reserved Interrupt Line Interrupt Pin Minimum Grant Maximum Latency Intel Reserved Power Management Capabilities ID Power Management Capabilities Power Management Control Intel Reserved Software SMI Interface Intel Reserved Register Description 10. Default Value Access 8086h RO 2572h RO 0000h RO,R/W 0090h RO,R/WC ...
Page 102
... The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identify any PCI device. Bit 15:0 Vendor Identification Number—RO. This is a 16-bit value assigned to Intel. 3.7.2 DID2—Device Identification Register (Device 2) Address Offset: ...
Page 103
... Memory Access Enable (MAE)R/W. This bit controls the IGD’s response to memory space accesses Disable (default Enable. I/O Access Enable (IOAE)R/W. This bit controls the IGD’s response to I/O space accesses Disable (default Enable. ® Intel 82865G/82865GV GMCH Datasheet 04h−05h 0000h RO, R/W 16 bits Description Register Description 103 ...
Page 104
... Bit Revision Identification Number—RO. This is an 8-bit value that indicates the revision identification number for the IGD. 7:0 02h = A-2 Stepping 104 06h−07h 0090h RO, R/WC 16 bits Description 08h See table below RO 8 bits Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 105
... Access: Size: The IGD does not support the programmability of the master latency timer because it does not perform bursts. Bit 7:0 Master Latency Timer Count Value—RO. Hardwired to 00h. ® Intel 82865G/82865GV GMCH Datasheet 09h−0Bh 030000h RO 24 bits Description 0Ch 00h ...
Page 106
... Address Mask—RO. Hardwired indicate (at least) a 32-MB address range. 3 Prefetchable Memory—RO. Hardwired enable prefetching. 2:1 Memory Type—RO. Hardwired indicate 32-bit address. 0 Memory/IO Space—RO. Hardwired indicate memory space. 106 0Eh 00h RO 8 bits Description 10–13h 00000008h R/ bits Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 107
... I/O Base Address—R/W. This field is set by the OS. These bits correspond to address signals 15:3 15:3. They provide the 16-bit I/O base address for the I/O registers. 2:1 Memory TypeRO. Hardwired indicate 32-bit address. 0 I/O SpaceRO. Hardwired indicate I/O space. ® Intel 82865G/82865GV GMCH Datasheet 14−17h 00000000h R/ bits Description 18−1Bh ...
Page 108
... Address MaskRO. Hardwired indicate 256-KB address range. 10:1 Reserved. Hardwired to 0s. ROM BIOS Enable—RO ROM not accessible. 108 2C–2Dh 0000h R/WO 16 bit Description 2E−2Fh 0000h R/WO 16 bits Description 30−33h 00000000h RO 32 bits Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 109
... INTRPIN—Interrupt Pin Register (Device 2) Address Offset: Default Value: Access: Size: Bit Interrupt Pin—RO single function device, the IGD specifies INTA# as its interrupt pin. 7:0 01h = INTA#. ® Intel 82865G/82865GV GMCH Datasheet 34h D0h RO 8 bits Description 3Ch 00h R/W ...
Page 110
... CAP_ID—RO. SIG defines this ID as 01h for power management. 110 3Eh 00h RO 8 bits Description 3Fh 00h RO 8 bits Description D0h−D1h 0001h RO 16 bits Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 111
... D0 (Default) 1 (Not Supported– Writes will be blocked and will return the previous value (Not Supported– Writes will be blocked and will return the previous value ® Intel 82865G/82865GV GMCH Datasheet D2h−D3h 0021h RO 16 bits Description D4h− ...
Page 112
... Graphics software and the System BIOS. These bits have no functional impact on the GMCH. (default = 0s) Software SMI Trigger—R/W. When this bit transitions from the GMCH will generate an SMI 0 message over HI. The SMI handler (software) must clear this bit by writing it. (default = 0). 112 E0h–E1h 0000h 16 bits R/W Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 113
... I/O Limit Address Secondary Status Memory Base Address Memory Limit Address Prefetchable Memory Base Limit Address Prefetchable Memory Limit Address Reserved Bridge Control Reserved Error Command Reserved CSA Control Intel Reserved Register Description Default Value Access 8086h RO 2573h RO 0000h RO,R/W 00A0h RO,R/WC ...
Page 114
... The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identify any PCI device. Bit 15:0 Vendor Identification Number—RO. This is a 16-bit value assigned to Intel. 3.8.2 DID3—Device Identification Register (Device 3) Address Offset: ...
Page 115
... Disable (default Enable. I/O Access Enable (IOAE)R/W. This bit must be set enable the I/O address range defined in the IOBASE3 and IOLIMIT3 registers Disable (default Enable. ® Intel 82865G/82865GV GMCH Datasheet 04h−05h 0000h RO, R/W 16 bits Description Register Description 115 ...
Page 116
... GMCH does not support any parity detection on the primary side of this device). Fast Back-to-Back (FB2B)—RO. Hardwired to 1. The interface always supports fast back-to-back 7 writes. 6 Reserved. 5 66/60 MHz PCI Capable (CAP66)—RO. Hardwired to 1. CSA is 66 MHz capable. 4:0 Reserved. 116 06h−07h 00A0h RO, R/WC 16 bits Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 117
... This register contains the Base Class Code of the GMCH Device 3. Bit Base Class Code (BASEC)—RO. This is an 8-bit value that indicates the Base Class Code for the GMCH Device 3. 7:0 06h = Bridge device. ® Intel 82865G/82865GV GMCH Datasheet 08h See table below RO 8 bits Description ...
Page 118
... Since Device internal device and its primary bus is always 0, these bits are read only and are hardwired to 00h. 118 0Dh 00h RO bits Description 0Eh 01h RO 8 bits Description 18h 00h RO 8 bits Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 119
... CSA. 3.8.12 SMLT3—Secondary Bus Master Latency Timer Register (Device 3) Address Offset: Default Value: Access: Size: Bit 7:0 Reserved. ® Intel 82865G/82865GV GMCH Datasheet 19h 00h R/W 8 bits Description 1Bh 00h RO 8 bits Description Register Description ...
Page 120
... I/O Address Limit (IOLIMIT)—R/W. This field corresponds to A[15:12] of the I/O address limit of 7:4 Device 3. Devices between this upper limit and IOBASE3 will be passed to CSA. 3:0 Reserved. 120 1Ch F0h RO, R/W 8 bits Description 1Dh 00h RO bits Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 121
... Fast Back-to-Back (FB2B)—RO. Hardwired to 1. GMCH target, supports fast back-to-back 7 transactions on CSA. 6 Reserved. 5 66/60 MHz PCI Capable (CAP66)—RO. Hardwired to 1. CSA is 66 MHz capable. 4:0 Reserved. ® Intel 82865G/82865GV GMCH Datasheet 1E–1Fh 02A0h RO, RWC 16 bits Description Register Description 121 ...
Page 122
... Bit Memory Address Limit (MLIMIT)— R/W. This field corresponds to A[31:20] of the lower limit of 15:4 the memory range that will be passed by Device 3 bridge to CSA. 3:0 Reserved. 122 20–21h FFF0h RO bits Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 123
... Memory Address Limit (MLIMIT)—R/W. This field corresponds to A[31:20] of the memory address 15:4 that corresponds to the upper limit of the range of memory accesses that will be passed by the Device 3 bridge to CSA. 3:0 Reserved. ® Intel 82865G/82865GV GMCH Datasheet 22–23h 0000h RO, R/W 16 bits Description ...
Page 124
... Bit Prefetchable Memory Address Limit (PMLIMIT)—R/W. This field corresponds to A[31:20] of the 15:4 upper limit of the address range passed by bridge Device 3 across CSA. 3:0 Reserved. 124 24−25h FFF0h R/ bits Description 26−27h 0000h R/ bits Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 125
... Parity Error Response Enable (PEREN)—RO. Hardwired to 0. The bit field definitions for VGAEN and MDAP are detailed in Table 12. VGAEN and MDAP Definitions VGAEN MDAP ® Intel 82865G/82865GV GMCH Datasheet 3Eh 00h R/ bits Description 0 All References to MDA and VGA space are routed to HI. 1 Illegal combination ...
Page 126
... Last Subordinate CSA (CSA_SUB_LAST)—R/W. This field stores the highest subordinate CSA 27:25 hub number. 24:16 Reserved. CSA Width (CSA_WIDTH)—R/W. This field describes the used width of the data bus bit 15: Reserved 10 = Reserved 11 = Reserved 13:0 Intel Reserved. 126 40h 00h R/ bits Description 50–53h 0E042802h R/ bits Description ® ...
Page 127
... The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification register, uniquely identifies any PCI device. Bit Vendor Identification (VID)—RO. This register field contains the PCI standard identification for 15:0 Intel, 8086h. ® Intel 82865G/82865GV GMCH Datasheet Table 13 provides the configuration register address map ...
Page 128
... Disable (default Enable. I/O Access Enable (IOAE) R/W. This bit must be set enable the I/O address range defined in the IOBASE3 and IOLIMIT3 registers Disable (default Enable. 128 02–03h 2576h RO 16 bits Descriptions 04–05h 0000h RO, R/W 16 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 129
... Bit Revision Identification Number (RID)—RO. This is an 8-bit value that indicates the revision identification number for the GMCH Device 6. This value is the same as the RID register. 7:0 02h = A-2 Stepping ® Intel 82865G/82865GV GMCH Datasheet 06–07h 0080h RO 16 bits Descriptions ...
Page 130
... This register identifies the header layout of the configuration space. Bit 7:0 PCI Header (HDR)—RO. This field indicates a single function device with standard header layout. 130 0Ah 80h RO 8 bits Descriptions 0Bh 08h RO 8 bits Descriptions 0Eh 00h RO 8 bits Descriptions ® Intel 82865G/82865GV GMCH Datasheet ...
Page 131
... Default Value: Access: Size: This value is used to identify a particular subsystem. Bit Subsystem ID (SUBID)—R/WO. This field should be programmed during BIOS initialization. After it 15:0 has been written once, it becomes read only. ® Intel 82865G/82865GV GMCH Datasheet 10–13h 00000000h RO, R/W 32 bits Descriptions 2C–2Dh 0000h ...
Page 132
... DRAM Row 0,1 Attribute DRAM Row 2,3 Attribute DRAM Row 4,5 Attribute DRAM Row 6,7 Attribute — Intel Reserved DRAM Timing — Intel Reserved DRAM Controller Mode — Intel Reserved 0000h–0007h (DRB0–DRB7) 00h R/W 8 bits each register Default Value Access 01h RW 01h RW ...
Page 133
... DRAM Row Boundary Address—R/W. This 7-bit value defines the upper and lower addresses for each SDRAM row. This 7-bit value is compared against address lines 0,31:26 (0 concatenated with 6:0 the address bits 31:26) to determine which row the incoming address is directed. Default= 0000001b ® Intel 82865G/82865GV GMCH Datasheet Register Description Description 133 ...
Page 134
... Row Attribute for Row 1 Rsvd 4 Row Attribute for Row 3 Rsvd 4 Row Attribute for Row 5 Rsvd 4 Row Attribute for Row 7 Rsvd Description 3 2 Row Attribute for Row Row Attribute for Row Row Attribute for Row Row Attribute for Row 6 ® Intel 82865G/82865GV GMCH Datasheet ...
Page 135
... DRAM RAS# Precharge (t between a precharge command and an activate command to the same bank DRAM clocks (DDR 333) 1 DRAM clocks DRAM clocks 11 = Reserved ® Intel 82865G/82865GV GMCH Datasheet 0060h–0063h 00000000h R/W 32 bits Description ) Max—R/W. These bits control the number of DRAM clocks for RAS (max µ ...
Page 136
... Refresh enabled. Refresh interval 15.6 µsec 10:8 010 = Refresh enabled. Refresh interval 7.8 µsec 011 = Refresh enabled. Refresh interval 64 µsec 111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Other = Reserved 7 Reserved. 136 0068h–006Bh 00000001h R/ bits Description ® Intel 82865G/82865GV GMCH Datasheet ...
Page 137
... Refresh Enable – In this mode all processor cycles to SDRAM result in a CBR cycle on the SDRAM interface 111 =Normal operation 3:2 Reserved DRAM Type (DT)—RO. This field is used to select between supported SDRAM types Reserved 1 Dual Data Rate SDRAM Other = Reserved. ® Intel 82865G/82865GV GMCH Datasheet Register Description Description 137 ...
Page 138
... Register Description 138 This page is intentionally left blank. ® Intel 82865G/82865GV GMCH Datasheet ...
Page 139
... BIOS or system designers responsibility to limit memory population so that adequate PCI, AGP, High BIOS, and APIC memory space can be allocated. simplified system memory address map. memory regions as defined and supported by the GMCH. ® Intel 82865G/82865GV GMCH Datasheet System Address Map Figure 9 Figure 10 ...
Page 140
... Memory Address Independently Programmable Range Max Top of the Main Memory FLASH APIC Reserved *Contains AGP Window, GFX Apeture, PCI and ICH ranges TOP of DRAM Intel Reserved TOUD(OS Visible Main Memory Optional ISA Hole Optionally mapped to the internal AGP 640 ® Intel ...
Page 141
... Intel 82865G/82865GV GMCH Datasheet Attributes Fixed: always mapped to main 0 to 640 KB – DOS Region SDRAM Mapped to hub interface, AGP, or Video Buffer (physical SDRAM IGD: configurable as SMM space ...
Page 142
... This area is a single, 64-KB segment. This segment can be assigned read and write attributes default (after reset) read/write disabled and cycles are forwarded to the hub interface. By manipulating the read/write attributes, the GMCH can “shadow” BIOS into the main system memory. When disabled, this segment is not remapped. 142 ® Intel 82865G/82865GV GMCH Datasheet ...
Page 143
... SDRAM memory disabled by opening the hole is not remapped to the Top of the memory – that physical SDRAM space is not accessible. This 15-MB–16-MB hole is an optionally enabled ISA hole. Video accelerators originally used this hole. There is no inherent BIOS request for the 15-MB–16-MB hole. ® Intel 82865G/82865GV GMCH Datasheet System Address Map 143 ...
Page 144
... SDRAM minus the value in the TSEG register. 144 Attributes R/W Available System Memory 62.5 MB SMM Mode Only - processor Reads TSEG Address Range SMM Mode Only - processor Reads TSEG Pre-allocated Memory Pre-allocated Graphics VGA memory. R (or 512 MB) when IGD is enabled. ® Intel Comments 82865G/82865GV GMCH Datasheet ...
Page 145
... The actual address space required for the BIOS is less than 2 MB but the minimum processor MTRR range for this region that the full 2 MB must be considered. ® Intel 82865G/82865GV GMCH Datasheet System Address Map 145 ...
Page 146
... PCI devices. The PCICMD1 register can override the routing of memory accesses to AGP. In other words, the memory access enable bit must be set in the device 1 PCICMD1 register to enable the memory base/limit and prefetchable base/limit windows. 146 ® Intel 82865G/82865GV GMCH Datasheet ...
Page 147
... This decreases the worst-case power consumption of the GMCH. DINV[3:0]# indicate if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase: DINV[3:0]# DINV0# DINV1# DINV2# DINV3# ® Intel 82865G/82865GV GMCH Datasheet Data Bits HD[15:0]# HD[31:16]# HD[47:32]# HD[63:48]# Functional Description 5 ...
Page 148
... Once posted, the memory write from PCI or hub interface to address 0FEEx_xxxxh is decoded as a cycle that needs to be propagated by the GMCH to the FSB as an Interrupt Message Transaction. 148 ® Intel 82865G/82865GV GMCH Datasheet ...
Page 149
... NOTE: The Smallest Increments column also represents the smallest possible single DIMM capacity. DIMM population guidelines are shown in Figure 11. Single-Channel Mode Operation CH A GMCH Mode Only Figure 12. Dual-Channel Mode Operation CH A GMCH CH B ® Intel 82865G/82865GV GMCH Datasheet Smallest Largest Increments Increments 64 MB 256 MB 128 MB 512 MB 256 MB 1024 MB ...
Page 150
... Special cases – need to meet few requirements discussed in 150 Dynamic Addressing Mode (1) Channel A Only Yes (1) Channel B Only Yes (1) Both Channel A and B Yes Linear Yes Tiled Yes Section Intel Table 18 Non-Dynamic Addressing Mode Yes Yes Yes (1) Yes (1) Yes 5.2.2.1. ® 82865G/82865GV GMCH Datasheet ...
Page 151
... Technology 512 Mbit – 64Mx8 – page size – row size of 512 MB Note: In Table 19 through The table cell contents refers to host address signals HAx. ® Intel 82865G/82865GV GMCH Datasheet Table 24 A0, A1, … refers to memory address MA0, MA1, …. Functional Description Table 19 ...
Page 152
... Col 256MB Row 256Mb 32Mx8 13x10x2 8KB Col 256MB Row 512Mb 32Mx16 13x10x2 8KB Col 512MB Row 512Mb 64Mx8 13x11x2 16KB Col 152 Addr BA1 BA0 A12 A11 A10 Addr BA1 BA0 A12 A11 A10 ® Intel 82865G/82865GV GMCH Datasheet ...
Page 153
... Col 128MB Row 256Mb 16Mx16 13x9x2 4KB Col 256MB Row 256Mb 32Mx8 13x10x2 8KB Col 256MB Row 512Mb 32Mx16 13x10x2 8KB Col 512MB Row 512Mb 64Mx8 13x11x2 16KB Col ® Intel 82865G/82865GV GMCH Datasheet Addr BA1 BA0 A12 A11 A10 ...
Page 154
... Col 128MB Row 256Mb 16Mx16 13x9x2 4KB Col 256MB Row 256Mb 32Mx8 13x10x2 8KB Col 256MB Row 512Mb 32Mx16 13x10x2 8KB Col 512MB Row 512Mb 64Mx8 13x11x2 16KB Col 154 Addr BA1 BA0 A12 A11 A10 Intel ...
Page 155
... Col 128MB Row 256Mb 16Mx16 13x9x2 4KB Col 256MB Row 256Mb 32Mx8 13x10x2 8KB Col 256MB Row 512Mb 32Mx16 13x10x2 8KB Col 512MB Row 512Mb 64Mx8 13x11x2 16KB Col ® Intel 82865G/82865GV GMCH Datasheet Addr BA1 BA0 A12 A11 A10 ...
Page 156
... Addr BA1 BA0 A12 A11 A10 Table 25 lists the supported configurations. Note that the GMCH 128 Mbit 256 Mbit x8 x16 x8 SS/DS SS/DS SS/DS 128/256 MB 64 MB/NA 256/512 512 Mbit x16 x8 SS/DS SS/DS SS/DS 128 MB/NA 512/1024 MB 256 MB/NA ® Intel 82865G/82865GV GMCH Datasheet x16 ...
Page 157
... Number of banks of SDRAM (single- or double-sided DIMM) 11 ECC, non-ECC (865G chipset GMCH does not support ECC) 12 Refresh rate 17 Number of banks on each device ® Intel 82865G/82865GV GMCH Datasheet ® 82801EB I/O Controller Hub 5 (ICH5) and Intel Function Functional Description ® 82801ER Table 26 lists a subset of 157 ...
Page 158
... DVO ports are not available as the GMCH’s IGD will be disabled. For more information on the multiplexed DVO interface, see See the AGP Revision 3.0 specification for additional details about the AGP interface. 158 Section 5.5.2. ® Intel 82865G/82865GV GMCH Datasheet ...
Page 159
... This is referred as “downshift” mode. Since AGP 2X is not supported, any card falling back to 2X will be running in a non supported mode. When in AGP 3.0 mode in the 4X data rate, all of the AGP 3.0 protocols are used. ® Intel 82865G/82865GV GMCH Datasheet AGP 3.0 AGP 2.0 ...
Page 160
... Strobe StrobeFirst Strobe# StrobeSecond No Disabled on xmit Yes No AGP 2.0 commands AGP 3.0 commands No (Not supported) No Yes ® Intel 82865G/82865GV GMCH Datasheet AGP 3.0 Signaling (8X Data Rate) 8X 0.35 V 3.0 signaling (0.8 V swing) Active high inverted (000 = idle) GC#/BE StrobeFirst StrobeSecond Yes No AGP 3.0 commands ...
Page 161
... AGP 3.0 detect = 1. To work correctly when AGP 3.0 detect = 1, AGP must be selected over DVO (i.e., when AGP 3.0 detect = 1, AGP/DVO# strap value must also be 1, regardless of the value on GPAR). Table 29. Pin and Strap Values Selecting Intel Card Plugged Into AGP ...
Page 162
... ISOCH Write, Fenced (NOT SUPPORTED) Reserved Reserved Flush Reserved) Fence (for reads and writes) Reserved (was DAC cycle) Isoch Align (NOT SUPPORTED) Reserved Signaling Level 1.5 V 3.3 V Yes No Yes No See Note No Yes ® Intel Table 30. AGP 3.0 Command 82865G/82865GV GMCH Datasheet ...
Page 163
... PCI Semantic Transactions on AGP The GMCH accepts and generates PCI semantic transactions on the AGP bus. The GMCH guarantees that PCI semantic accesses to SDRAM are kept coherent with the processor caches by generating snoops to the processor bus. ® Intel 82865G/82865GV GMCH Datasheet Functional Description 163 ...
Page 164
... High bandwidth access to data is provided through the graphics and system memory ports. The GMCH can access graphics data located in system memory at 2.1 GB/s – 6.4 GB/s (depending on memory configuration). The GMCH uses Intel’s Direct Memory Execution model to fetch textures from system memory. The GMCH includes a cache controller to avoid frequent memory fetches of recently used texture data ...
Page 165
... The scissor rectangle needs to be pixel accurate, and independent of line and point width. The GMCH supports a single scissor box rectangle that can be enabled or disabled. The rectangle is defined as an Inclusive box. Inclusive is defined as “draw the pixel inside the scissor rectangle”. ® Intel 82865G/82865GV GMCH Datasheet Functional Description 165 ...
Page 166
... A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon. A texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in perspective important that texture be mapped in perspective as well. Without perspective correction, texture is distorted when an object recedes into the distance. 166 ® Intel 82865G/82865GV GMCH Datasheet ...
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... LODs are selected and within each LOD the texel with coordinates nearest to the desired pixel are selected. The Final texture value is generated by linear interpolation between the two texels selected from each of the MIP Maps. ® Intel 82865G/82865GV GMCH Datasheet Functional Description 167 ...
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... These specular highlighted, fogged, textured pixels are color blended with the existing values in the frame buffer. In parallel, stencil, alpha, and depth buffer tests are conducted that will determine whether the Frame and Depth Buffers will be updated with the new pixel values. 168 ® Intel 82865G/82865GV GMCH Datasheet ...
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... It adds another level of realism to computer-generated scenes. Fog can be used for depth cueing or hiding distant objects. With fog, distant objects can be rendered with fewer details (less polygons), thereby improving the rendering speed or frame rate. Fog is simulated by attenuating ® Intel 82865G/82865GV GMCH Datasheet Functional Description 169 ...
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... The Instruction set of the GMCH provides a variety of controls for the buffers (e.g., initializing, flip, clear, etc.). 170 and alpha (A ) component with a destination pixel color component. For example, this is so that a glass surface on top (source) D Intel ® 82865G/82865GV GMCH Datasheet ...
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... The GMCH supports two, simultaneous projective textures at full rate processing, and four textures at half rate. These textures require three floating point texture coordinates to be included in the FVF format. Projective textures enable special effects (e.g., projecting spot light textures obliquely onto walls, etc.). ® Intel 82865G/82865GV GMCH Datasheet Functional Description 171 ...
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... GMCH VGA Registers The 2D registers are a combination of registers defined by IBM when the Video Graphics Array (VGA) was first introduced and others that Intel has added to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard ...
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... Cursor Plane The cursor plane is one of the simplest display planes. With a few exceptions, this plane has a fixed size of 64x64 and a fixed Z-order (top). In legacy modes, cursor can cause the display data below inverted. ® Intel 82865G/82865GV GMCH Datasheet Functional Description 173 ...
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... This is the best solution for images with motion; however, it will have reduced spatial resolution in areas that have no motion and introduces jaggies. In absence of any other deinterlacing, these form the baseline and are supported by the GMCH. 174 ® Intel 82865G/82865GV GMCH Datasheet ...
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... The GMCH is compliant with Digital Visual Interface (DVI) Specification, Revision 1.0. When combined with a DVI compliant external device and connector, the GMCH has a high-speed interface to a digital display (e.g., flat panel or digital CRT). ® Intel 82865G/82865GV GMCH Datasheet Functional Description 175 ...
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... No No 3.3 V Port control VGA or port control Externally buffered Through GPIO interface Digital Port C DVO 2.0 DVO 2.0 (1) (1) Yes Yes Yes Yes Yes Yes (1) Yes 1.5 V 1.5 V Differential 165/330 Mpixel RGB 8:8:8 YUV 4:4:4 DDC2B ® Intel 82865G/82865GV GMCH Datasheet ...
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... These additional digital display capabilities may be provided through an ADD card that is designed to plug 1.5 V AGP connector. 5.5.2.1 Digital Display Channels – Intel The GMCH has the capability to support digital display devices through two DVO ports multiplexed with the AGP signals. When an external graphics accelerator is used via AGP, these DVO ports are not available ...
Page 178
... The overscan compensation scaling and the flicker filter is done in the external TV encoder chip. Care must be taken to allow for support of TV sets with high performance de-interlacers and progressive scan displays connected to by way of a non-interlaced signal. Timing will be generated with pixel granularity to allow more overscan ratios to be supported. 178 ® Intel 82865G/82865GV GMCH Datasheet ...
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... As in high-low mode, 2 full pixels are transferred per clock period. This ordering can be modified through DVO control registers. ® Intel 82865G/82865GV GMCH Datasheet Functional Description 2 C bus to interrogate the external ...
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... Processor — C0 — C1 — C2-Desktop 180 Full on, display active. GMCH power on. Display off. Configuration registers, state, and main memory contents retained. Power off. Full On. Auto Halt. Stop Grant. Clk to processor still running. Clock stopped to processor core. Intel ® 82865G/82865GV GMCH Datasheet ...
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... DIMM(s) is the source of the over-temp through the serial interface. However, since the DIMMs are located on the same memory bus data lines, any GMCH-base read throttle will apply equally. ® Intel 82865G/82865GV GMCH Datasheet Full On. Stop Grant, Desktop S1, same as C2. ...
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... Characterization tools (e.g., CTMI and Maxband) can be made to work either with external or internal sensors. 182 EXTTS# GMCH THERM ® Intel ICH5 SMBus ® Intel 82865G/82865GV GMCH Datasheet V R (1) SMBdata SMBclock ...
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... AGP and hub interface are synchronous to each other and are driven from the 66 MHz clock. The Graphics core and display interfaces are asynchronous to the rest of the GMCH. ® Figure 15. Intel 865G Chipset System Clocking Block Diagram Low Voltage Differential Clocks Low Voltage Differential Clocks ...
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... Functional Description 184 This page is intentionally left blank. ® Intel 82865G/82865GV GMCH Datasheet ...
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... VTT VCC_DDR VCCA_DDR VCC_DAC VCCA_DAC VCCA_DPLL VCCA_FSB 6.2 Thermal Characteristics ® Refer to the Intel characteristics. ® Intel 82865G/82865GV GMCH Datasheet Parameter 1.5 V Core Supply 1.5 V AGP Supply (AGP mode) 1.5 V Analog AGP Supply VTT Supply 2.6 V DDR System Memory Interface Supply 1 ...
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... AGP 3.0 0.8V Signaling Environment DC and AC Specifications. The buffers are not 3.3 V tolerant. (DVO signals use the same buffers as AGP) Hub Interface 1.5 V CMOS buffers. Stub Series Terminated Logic 2.6 V compatible signals. DDR system memory 2.6 V CMOS buffers. 2.6 V and 3.3 V Miscellaneous buffers. Intel Max Unit Notes 4.38 A 1,2,3 2 ...
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... DDR Interface Signal Groups (l) DDR SSTL_2 I/O (m) DDR SSTL_2 Output (v) DDR RCOMP (n) DDR Miscellaneous ® Intel 82865G/82865GV GMCH Datasheet Signals GADSTBF[1:0], GADSTBS[1:0], GFRAME, GIRDY, GTRDY, GSTOP, GDEVSEL, GAD[31:0], GCBE[3:0], GPAR/ADD_DETECT, DBI_HI, DBI_LO GSBA[7:0]#, GRBF, GWBF, GSBSTBF, GSBSTBS, GREQ GST[2:0], GGNT GVREF, GRCOMP/DVOBCRCOMP, GVSWING ...
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... V Miscellaneous I/O (w) FSB Select Input (x) Clocks LVTTL NOTES: 1. For details on BSEL[1:0] pin electrical requirements, see the Intel Platform Design Guide. 2. For additional details on SMXRCOMP, SMYRCOMP, SMXRCOMPVOL, SMXRCOMPVOH, SMYRCOMPVOL, SMYRCOMPVOH pin electrical requirements, see the Intel Chipset Platform Design Guide. 188 ...
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... Table 37. DC Operating Characteristics (Sheet Signal Name Parameter I/O Buffer Supply Voltage VCC Core Voltage VCC_AGP AGP I/O Voltage VCCA_AGP AGP Analog Supply Voltage VTT (Intel® Pentium® 4 processor with Host AGTL+ Termination 512-KB L2 cache on Voltage 0.13 micron process) VTT (Intel® Pentium® 4 ...
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... SMVREF DDR Reference Voltage NOTES: ® 1. Refer to the Intel values used to calculate Vsh. For values pertaining to the Pentium 4 processor process, contact your Intel field representative. 2. HDVREF is generically referred to as GTLREF throughout the rest of this chapter. 3. SMXRCOMPVOL/SMYRCOMPVOL and SMXRCOMPVOH/SMYRCOMPVOH have maximum input leakage current ...
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... Hub Interface Output V (e) OH_HI High Voltage Hub Interface Input I (e) LEAK_HI Leakage Current Hub Interface Input C (e) IN_HI Capacitance ® Intel 82865G/82865GV GMCH Datasheet Min Nom 6 – 0.5 AGP_VREF – 0.15 AGP_VREF + 0.15 1.275 – 4.7 6 – 0.3 AGP_VREF + 0.10 ...
Page 192
... CI_VREF + 0.1 0.6 HDVREF HDVREF + (0.04*Vsh) 1/4* Vsh (Vsh-0.1) * 0.95 0.75 * Vshmax / Rttmin 1 – 0.1 * VCC_DDR SMVREF SMVREF + 0.15 – 0.1 * VCC_DDR SMVREF SMVREF + 0.31 VCC_DDR – 0.600 – 25 – 50 ® Intel Max Unit Notes V 1 0.8/R , OUT TT 1 Ω ± ...
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... Maximum leakage current specification for the GVREF pin is 65 uA. The Maximum leakage current specification for the GVSWING pin is 50 µA. Refer to Intel Design Guide for the resistor divider circuit details that take this specification into account. 7. Maximum leakage current specification for HI_VREF and HI_SWING pins is 50 µA. Refer to 865G/865GV/ 865PE/865P Chipset Platform Design Guide for the resistor divider circuit details that take this specification into account ...
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... Set by external reference resistor value. 6. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage). 6.6.2 DAC Reference and Output Specifications Table 40. DAC Reference and Output Specifications Parameter Reference resistor NOTE: ® 1. Refer to the Intel implementation. 194 Min Typical Max 8 0.665 0.700 ...
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... Noise Injection Ratio VCCA_DAC VCCA_DAC – 0. MHz VCCA_DAC – 0.9% 10 MHz to Pixel Clock Frequency NOTES: 1. Any deviation from this specification should be validated. Refer to the Intel Chipset Platform Design Guide for the VCCA_DAC filter circuit implementation. ® Intel 82865G/82865GV GMCH Datasheet Typical Max Units ...
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... Electrical Characteristics 196 This page is intentionally left blank. ® Intel 82865G/82865GV GMCH Datasheet ...
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... For AGP signals, only the AGP 3.0 signal name is listed. For the corresponding AGP 2.0 signal name, refer Connect. 4. RSVD = These reserved balls should not be connected and should be allowed to float. 5. Shaded cells in ® Intel 82865G/82865GV GMCH Datasheet Figure 16 and Figure 17. These figures represent the ballout Table 42 provides the ballout arranged alphabetically by signal name ...
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... Ballout and Package Information ® Figure 16. Intel 82865G GMCH Ballout Diagram (Top View—Left Side VSS VCC_DDR AP RSVD SDQ_A26 SMAB_A3 SMAB_A4 SDM_A3 AN RSVD SDQ_A31 VSS SMAA_A3 AM VSS SMAB_A2 SDQ_A27 SDQ_A30 SDQS_A3 AL VCCA_DDR SMAB_A1 SMAA_A1 VSS SMAA_A4 SMAB_B3 SMAA_A6 SMAB_B4 SMAA_A5 SMAA_B6 SDQ_A18 ...
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... Figure 17. Intel 82865G GMCH Ballout Diagram (Top View—Right Side VSS VCC_DDR VSS SCMD SDM_A1 SDQS_A1 SDQ_A8 SDQ_A7 SDM_A0 CLK_A1 SCMD VSS SDQ_A13 VSS SDQ_A3 VSS CLK_A1# SCMD VSS VSS SDQ_A9 VSS SDQ_A2 CLK_A4 SCMD SCMD SDQ_B11 SDQ_A12 SDQ_B9 SDQ_A6 ...
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... Ballout and Package Information 200 This page is intentionally left blank. ® Intel 82865G/82865GV GMCH Datasheet ...