E7804BHF Semtech, E7804BHF Datasheet - Page 6

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E7804BHF

Manufacturer Part Number
E7804BHF
Description
Manufacturer
Semtech
Datasheet

Specifications of E7804BHF

Operating Temperature (max)
100C
Package Type
MQFP
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
Introduction
The four driver and window comparator channels of the
E7804 are shown in Figure 1.
Driver
Refer to Table 1 showing the modes of operation of the
driver.
Each channel’s driver states of HiZ, force DVH voltage,
force DVL voltage and Open can be controlled either by
external input pins or via internal registers and bits
programmed through the serial interface.
The HiZ/DVH/DVL states are controlled by the differential,
external inputs, DHI/DHI* and DEN/DEN*. Each channel
also has internal register bits (see Table 2,
CH[0:3]_Relays_&_States registers) SDHI and SDEN that
accomplish the same functions as DHI and DEN. The serial
register has another bit, SEN (Serial Enable) that allows
the SDI and SDEN bits to override the external input pins
DHI and DEN. If SEN is a logical “0”, the SDHI and SDEN
bits are ignored.
The DHI/DHI* and DEN/DEN* inputs are LV_TTL and
differential LVDS, LV_PECL compatible.
Unused DHI/DHI* or DEN/DEN* must be tied to valid logic
levels.
Optimizing Driver Waveforms
The driver output pin, VIO, will normally be connected to
the parametric output pin, POUT, when designed into a
system. See the recommended 7804 Hookup drawing
farther on in this datasheet. The POUT pin has a lumped
capacitance associated with it that will degrade the signal
integrity of the driver output waveform if not properly
compensated for. The recommendation is to insert ferrite
devices between the connection of POUT to VIO to
accomplish this. For more details on how and why this
approach is used, please read Semtech Application Note
#ATE-A3 ATE-to-DUT Interface: Using Ferrites to Replace
Relays for Lower Cost and Improved Performance.
The driver output impedance has a reactive component
to it and will not completely absorb reflections from an
unterminated transmission line. This is common for all
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
2005 Semtech Corp. / Rev. 5, 12/6/05
6
drivers, but more so in CMOS drivers than high speed
bipolar stages. The figure here shows how transmission
line length, here in the form of coaxial cable, will sum the
reflections constructively and destructively to alter the
peak-to-peak waveform excursions across frequency.
More data on this performance and methods for optimizing
signal integrity and extending Fmax will be available from
Semtech staff. Check with Semtech for the latest
information. From the graph below one can see that
E7804 driver signals in excess of 150MHz are possible.
Driver Levels
Each channel’s DVH and DVL are high input impedance
voltage inputs which establish the channel driver’s high
and low levels. The driver’s output range is –0.2V, +5.2V.
DVH to VIO and DVL to VIO offset errors are small, which
allow the Edge7804 to be configured with common input
levels to each channel (i.e. DVH[0:3] may be connected
together externally, and the same for DVL[0:3]).
Driver Source Impedance
Drivers feature a self-calibrating source impedance
calibrated to match an external resistor, R
between the EREF pin and analog ground. The source
impedance can be chosen to calibrate in the range 48
to 110
A driver’s source impedance is affected by its DVH and
DVL levels, and therefore needs recalibrating whenever
driver levels into the chip are changed. The calibration
routine is initiated via the serial interface (see Table 2,
calibrate_output_z register). When initiated, all channels
are recalibrated in parallel.
using the calculation R
EREF
/100.
Edge7804
PRELIMINARY
EREF
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, connected

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