CY8C5246AXI-054 Cypress Semiconductor Corp, CY8C5246AXI-054 Datasheet - Page 9

• Manufacturer Part Number: CY8C5246AXI-054
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5246AXI-054

• Lead Free Status / Rohs Status: Compliant

3. Pin Descriptions
IDAC0. Low resistance output pin for high current DAC (IDAC).
Extref0, Extref1. External reference input to the analog system.
GPIO. General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense
I2C0: SCL, I2C1: SCL. I
on an address match. Any I/O pin can be used for I
wake from sleep is not required.
I2C0: SDA, I2C1: SDA. I
on an address match. Any I/O pin can be used for I
wake from sleep is not required.
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33 MHz crystal oscillator
pin.
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO. Special I/O provides interfaces to the CPU, digital periph-
erals and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
SWDCK. Serial Wire Debug Clock programming and debug port
connection.
SWDIO. Serial Wire Debug Input and Output programming and
debug port connection.
TCK. JTAG Test Clock programming and debug port connection.
Document Number: 001-55034 Rev. *F
Note
4. GPIOs with OpAmp outputs are not recommended for use with CapSense.
Figure 2-4. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance
[4]
.
2
2
C SCL line providing wake from sleep
C SDA line providing wake from sleep
Plane
Vssd
PRELIMINARY
Vddd
2
2
C SDA if
C SCL if
Vssd
TDI. JTAG Test Data In programming and debug port
connection.
TDO. JTAG Test Data Out programming and debug port
connection.
TMS. JTAG Test Mode Select programming and debug port
connection.
TRACECLK. Cortex-M3
TRACEDATA pins.
TRACEDATA[3:0]. Cortex-M3
output data.
SWV. Single Wire Viewer output.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from Vddd instead
of from a Vddio. Pins are No Connect (NC) on devices without
USB.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from Vddd instead
of from a Vddio. Pins are No Connect (NC) on devices without
USB.
Vboost. Power sense connection to boost pump.
Vbat. Battery supply to boost pump.
Vcca. Output of analog core regulator and input to analog core.
Requires a 1 µF capacitor to Vssa. Regulator output not for
external use.
Vccd. Output of digital core regulator and input to digital core.
The two Vccd pins must be shorted together, with the trace
between them as short as possible, and a 1 µF capacitor to Vssd;
see
use.
PSoC
Vssa
Power System
[2]
[2]
Vdda
®
5: CY8C52 Family Data Sheet
on page 23. Regulator output not for external
Plane
Vssa
TRACEPORT
TRACEPORT
connection,
connections,
Page 9 of 88
clocks
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