CY7C4241V-25AC Cypress Semiconductor Corp, CY7C4241V-25AC Datasheet
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CY7C4241V-25AC
Specifications of CY7C4241V-25AC
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CY7C4241V-25AC Summary of contents
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... High-speed, low-power, first-in, first-out (FIFO) memories • (CY7C4421V) • 256 x 9 (CY7C4201V) • 512 x 9 (CY7C4211V) • (CY7C4221V) • (CY7C4231V) • (CY7C4241V) • (CY7C4251V) • High-speed 66-MHz operation (15-ns read/write cycle time) • Low power ( mA) CC • 3.3V operation for low power consumption and easy integration into low-voltage systems • ...
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... All configurations are fabricated using an advanced 0.65µ P-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. CY7C4231V/4241V/4251V CY7C42X1V-35 Unit 40 28.6 MHz CY7C4241V CY7C4251V Page [+] Feedback ...
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Architecture The CY7C42X1V consists of an array words of nine bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and ...
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... LOW when the number of unread words in the FIFO is greater than or equal to CY7C4421V (64 – m), CY7C4201V (256 – m), CY7C4211V (512 – m), CY7C4221V (1K – m), CY7C4231V (2K – m), CY7C4241V (4K – m), and CY7C4251V (8K – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m ...
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... Full Offset (m=7 default value). Document #: 38-06010 Rev. *B CY7C4421V/4201V/4211V/4221V CY7C4201V CY7C4211V 0 [ (n+1) to 256 257 to (512−(m+1)) [3] [3] to 255 (512−m) to 511 512 CY7C4241V CY7C4251V 0 0 [2] [ (n+1) to 2048 (n+1) to 4096 2049 to (4096 −(m+1)) 4097 to (8192 −(m+1)) [3] (4096−m) to 4095 (8192−m) ...
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RESET (RS) DATA IN ( WRITE CLOCK (WCLK) WRITE ENABLE 1 (WEN1) WRITE ENABLE 2/LOAD (WEN2/LD) CY7C42X1V PROGRAMMABLE (PAF) FULL FLAG (FF FULL FLAG (FF Read Enable 2 (REN2) Figure 2. Block Diagram ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ...................................–65 Ambient Temperature with Power Applied............................................. –-55 Supply Voltage to Ground Potential ............... –0.5V to +5.0V DC Voltage Applied to Outputs in ...
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Switching Characteristics Over the Operating Range Parameter Description t Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock HIGH Time CLKH t Clock LOW Time CLKL t Data Set-Up Time DS t Data ...
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Switching Waveforms Write Cycle Timing t CLKH WCLK D – WEN1 WEN2 (if applicable) FF [11] t SKEW1 RCLK REN1,REN2 Read Cycle Timing t CLKH RCLK t t ENS ENH REN1,REN2 EF Q – OLZ ...
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Switching Waveforms (continued) [13] Reset Timing RS REN1, REN2 WEN1 [15] WEN2/LD EF,PAE FF,PAF − 8 Notes: 13. The clocks (RCLK, WCLK) can be free-running during reset. 14. After reset, the outputs will be LOW if OE ...
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Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLK –D D (FIRSTVALID WRITE ENS WEN1 WEN2 (if applicable) t SKEW1 RCLK EF REN1, REN2 Q –Q 0 ...
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Switching Waveforms (continued) Empty Flag Timing WCLK t DS DATAWRITE1 D – ENH WEN1 t ENS t t ENS ENH WEN2 (if applicable) t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER ...
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Switching Waveforms (continued) Full Flag Timing NO WRITE WCLK [11] t SKEW1 D – WFF FF WEN1 WEN2 (if applicable) RCLK t ENH t ENS REN1, REN2 LOW –Q DATA IN OUTPUT REGISTER ...
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... PAF offset = m. 23. 64–m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512–m words for CY7C4211V, 1024–m words for CY7C4221V, 2048–m words for CY7C4231V, 4096–m words for CY7C4241V, 8192–m words for CY7C4251V. 24 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge ...
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Switching Waveforms (continued) Read Programmable Registers t CLK t CLKH RCLK t ENS WEN2/LD t ENS REN1, REN2 Q – Ordering Information 256 x 9 Low Voltage Synchronous FIFO Speed (ns) Ordering Code Package Name 15 CY7C4201V-15AC CY7C4201V-15AXC ...
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... Ordering Information (continued Low Voltage Synchronous FIFO Speed (ns) Ordering Code Package Name 15 CY7C4241V-15AC CY7C4241V-15AXC CY7C4241V-15JXC CY7C4241V-15JC 25 CY7C4241V-25AC CY7C4241V-25AXC CY7C4241V-25JC Low Voltage Synchronous FIFO Speed (ns) Ordering Code Package Name 15 CY7C4251V-15AC CY7C4251V-15AXC CY7C4251V-15JC 25 CY7C4251V-25AC CY7C4251V-25AXC Package Diagrams 32-Lead Thin Plastic Quad Flatpack 1.0 mm A32 32-Lead Pb-Free Thin Plastic Quad Flatpack ...
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... Document #: 38-06010 Rev. *B © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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... Change from Spec number: 38-00622 to 38-06010 Fixed empty flag timing diagram Fixed switching waveform diagram typo Added Pb-Free logo to top of front page Inserted industrial temperature range into operating range Added parts CY7C4251V-25AXC, CY7C4251V-15AXC, CY7C4241V-15AXC, CY7C4241V-15JXC, CY7C4241V-25XC, CY7C4231V-25AXC, CY7C4221V-15AI, CY7C4211V-15AXI, CY7C4201V-15AXC to ordering information. CY7C4231V/4241V/4251V Page [+] Feedback ...