LTC4251-2CS6#PBF Linear Technology, LTC4251-2CS6#PBF Datasheet - Page 15

• Manufacturer Part Number: LTC4251-2CS6#PBF
• Manufacturer: Linear Technology

Specifications of LTC4251-2CS6#PBF

• Family Name: LTC4251-2
• Package Type: TSOT-23
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Height (mm): 0.9mm
• Product Length (mm): 2.9mm
• Mounting: Surface Mount
• Pin Count: 6
• Lead Free Status / Rohs Status: Compliant

APPLICATIO S I FOR ATIO
and V
bypass capacitor. At time point 2, V
the internal logic checks for V
TIMER < V
all conditions are met, an initial timing cycle starts and the
TIMER capacitor is charged by a 5.8µA current source
pull-up. At time point 3, TIMER reaches the V
old and the initial timing cycle terminates. The TIMER
capacitor is then quickly discharged. At time point 4, the
V
V
up cycle is allowed to begin. GATE sources 58µA into the
external MOSFET gate and compensation network. When
the GATE voltage reaches the MOSFET’s threshold,
current begins flowing into the load capacitor. At time
point 5, the SENSE voltage (V
threshold and activates the TIMER. The TIMER capacitor
is charged by a 230µA current-source pull-up. At time
point 6, the analog current limit loop activates. Between
time point 6 and time point 7, the GATE voltage is held
essentially constant and the sense voltage is regulated at
V
begins to decline. At point 7, the load current falls and the
sense voltage drops below V
loop shuts off and the GATE pin ramps further. At time
point 8, the sense voltage drops below V
now discharges through a 5.8µA current source pull-
down. At time point 9, GATE reaches its maximum voltage
as determined by V
Live Insertion with Short Pin Control of UV/OV
In this example as shown in Figure 8, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
connections are firmly established before the LTC4251/
LTC4251-1/LTC4251-2 are activated. At time point 1, the
power pins make contact and V
time point 2, the UV/OV divider makes contact and its
voltage exceeds V
checks for V
< V
an initial timing cycle starts and the TIMER capacitor is
charged by a 5.8µA current source pull-up. At time point
3, TIMER reaches the V
TMRL
GATEL
ACL
GATEL
. As the load capacitor nears full charge, its current
OUT
threshold is reached and the conditions of GATE <
and SENSE < V
. V
and SENSE < V
TMRL
UVHI
IN
follows at a slower rate as set by the V
, GATE < V
< UV/OV < V
UVHI
IN
U
.
CB
. In addition, the internal logic
CB
must be satisfied before a start-
TMRH
U
GATEL
. When all conditions are met,
ACL
SENSE
OVHI
IN
threshold and the initial
. The analog current limit
UVHI
and SENSE < V
ramps through V
, TIMER < V
– V
W
IN
< UV/OV < V
EE
exceeds V
) reaches the V
CB
TMRH
TMRL
and TIMER
U
CB
LKO
thresh-
. When
LKO
, GATE
OVLO
and
. At
CB
IN
,
timing cycle terminates. The TIMER capacitor is then
quickly discharged. At time point 4, the V
reached and the conditions of GATE < V
< V
to begin. GATE sources 58µA into the external MOSFET
gate and compensation network. When the GATE voltage
reaches the MOSFET’s threshold, current begins flowing
into the load capacitor. At time point 5, the SENSE voltage
(V
TIMER. The TIMER capacitor is charged by a 230µA
current source pull-up. At time point 6, the analog current
limit loop activates. Between time point 6 and time point 7,
the GATE voltage is held essentially constant and the
sense voltage is regulated at V
nears full charge, its current begins to decline. At time
point 7, the load current falls and the sense voltage drops
below V
GATE pin ramps further. At time point 8, the sense voltage
drops below V
5.8µA current source pull-down. At time point 9, GATE
reaches its maximum voltage as determined by V
Undervoltage Lockout Timing
In Figure 9, when UV/OV drops below V
TIMER and GATE pull low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV/OV recovers and clears V
initial time cycle begins followed by a start-up cycle.
Undervoltage Timing with Overvoltage Glitch
In Figure 10, when UV/OV clears V
initial timing cycle starts. If the system bus voltage over-
shoots V
At time point 3, the supply voltage recovers and drops
below the V
followed by a start-up cycle.
Overvoltage Timing
During normal operation, if UV/OV exceeds V
shown at time point 1 of Figure 11, the TIMER status is
unaffected. Nevertheless, GATE pulls down and discon-
nects the load. At time point 2, UV/OV recovers and drops
below the V
SENSE
CB
must be satisfied before a start-up cycle is allowed
ACL
– V
OVHI
EE
. The analog current limit loop shuts off and the
OVLO
OVLO
as shown at time point 2, TIMER discharges.
) reaches the V
LTC4251/LTC4251-1/
CB
threshold. The initial timing cycle restarts
threshold. A gate ramp up cycle ensues.
and TIMER now discharges through a
CB
threshold and activates the
ACL
. As the load capacitor
UVHI
UVHI
LTC4251-2
UVLO
GATEL
(time point 1), an
(time point 2), an
TMRL
(time point 1),
threshold is
and SENSE
OVHI
15
IN
425112fa
.
as