CYS25G0101DX-ATC Cypress Semiconductor Corp, CYS25G0101DX-ATC Datasheet - Page 6

• Manufacturer Part Number: CYS25G0101DX-ATC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYS25G0101DX-ATC

• Number Of Transmitters: 1
• Number Of Receivers: 1
• Power Supply Requirement: Single
• Package Type: TQFP
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / Rohs Status: Not Compliant

Table 1. CYS25G0101DX OC-48 SONET Transceiver (continued)
Document Number: 38-02009 Rev. *L
DIAGLOOP
LINELOOP
LOOPA
LOOPTIME
OUT±
IN±
V
V
V
V
V
Note
4. V
Loop Control Signals
Serial I/O
Power
CCN
SSN
CCQ
SSQ
DDQ
Pin Name
DDQ
equals V
LVTTL input
LVTTL input
LVTTL input
LVTTL input
Differential CML
output
Differential CML
input
Power
Ground
Power
Ground
Power
CC
I/O Characteristics
if interfacing to a parallel LVPECL interface.
Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive
clock and data recovery. It is then presented at the RXD[15:0] outputs. When LOW,
received serial data is routed through the receive clock and data recovery. It is then
presented at the RXD[15:0] outputs.
Line Loopback Control. When HIGH, received serial data is looped back from receive to
transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data
passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA
are LOW, the data passed to the OUT± line driver is generated in the transmit shifter.
Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial
data is looped back from receive input buffer to transmit output buffer but is not routed
through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the
OUT± line driver is controlled by LINELOOP.
Loop Time Mode. When HIGH, the extracted receive bit clock replaces transmit bit clock.
When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock.
Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable
of driving terminated 50
Differential Serial Data Input. This differential input accepts the serial data stream for
deserialization and clock extraction.
+3.3V supply (for digital and low speed IO functions)
Signal and power ground (for digital and low speed IO functions)
+3.3V quiet power (for analog functions)
Quiet ground (for analog functions)
+1.5V supply for HSTL outputs
Ω
transmission lines or commercial fiber optic transmitter modules.
[4]
Signal Description
CYS25G0101DX
Page 6 of 18
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