AD5754AREZ Analog Devices Inc, AD5754AREZ Datasheet - Page 5

• Manufacturer Part Number: AD5754AREZ
• Description: IC DAC 16BIT DSP/SRL 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5754AREZ

• Data Interface: Serial
• Design Resources: Software Configurable 16-Bit Quad-Channel Unipolar/Bipolar Voltage Output Using AD5754 (CN0086)
• Settling Time: 10µs
• Number Of Bits: 16
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 310mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Resolution (bits): 16bit
• Sampling Rate: 100kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Supply Current: 2.5mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC PERFORMANCE CHARACTERISTICS
AV
C
Table 2.
Parameter
DYNAMIC PERFORMANCE
1
2
TIMING CHARACTERISTICS
AV
all specifications T
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
For specified performance, maximum headroom requirement is 0.9 V.
Guaranteed by design and characterization. Not production tested.
Guaranteed by characterization; not production tested.
All input signals are specified with t
See Figure 2, Figure 3, and Figure 4.
Daisy-chain and readback mode.
C
LOAD
4
4
L SDO
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Crosstalk
DAC-to-DAC Crosstalk
Digital Feedthrough
Output Noise
Output Noise Spectral Density
DD
DD
0.1 Hz to 10 Hz Bandwidth)
100 kHz Bandwidth
= capacitive load on SDO output.
= 4.5 V to 16.5 V; AV
= 4.5 V
= 200 pF; all specifications T
2
1, 2, 3
1
to 16.5 V; AV
MIN
to T
Limit at t
33
13
13
13
13
100
5
0
20
20
20
10
20
2.5
13
40
200
MAX
SS
SS
= −4.5 V to −16.5 V, or 0 V; GND = 0 V; REFIN = 2.5 V; DV
, unless otherwise noted.
= −4.5 V
R
= t
MIN
F
= 5 ns (10% to 90% of DV
MIN
, t
MAX
to T
1
to −16.5 V, or 0 V; GND = 0 V; REFIN= 2.5 V; DV
MAX
.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs typ
ns min
µs max
ns min
ns max
ns min
CC
Min
) and timed from a voltage level of 1.2 V.
A, B Version
Rev. C | Page 5 of 32
Typ
10
7.5
3.5
13
35
10
10
0.6
15
80
320
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (write mode)
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
DAC output settling time
CLR pulse width low
CLR pulse activation time
SYNC rising edge to SCLK rising edge
SCLK rising edge to SDO valid (C
Minimum SYNC high time (readback/daisy-chain mode)
Max
12
8.5
5
Unit
µs
µs
µs
V/µs
nV-sec
mV
nV-sec
nV-sec
nV-sec
µV p-p
µV rms
nV/√Hz
CC
= 2.7 V to 5.5 V; R
CC
= 2.7 V to 5.5 V; R
Test Conditions/Comments
20 V step to ±0.03% FSR
10 V step to ±0.03% FSR
512 LSB step settling (16-bit resolution)
0x8000 DAC code
Measured at 10 kHz, 0x8000 DAC code
L SDO
AD5724/AD5734/AD5754
5
= 15 pF)
LOAD
LOAD
= 2 kΩ; C
= 2 kΩ;
LOAD
= 200 pF;