AD5545BRUZ Analog Devices Inc, AD5545BRUZ Datasheet - Page 11

• Manufacturer Part Number: AD5545BRUZ
• Description: IC DAC 16BIT DUAL SRL IN 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5545BRUZ

• Data Interface: Serial
• Settling Time: 500ns
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 16bit
• Sampling Rate: 2MSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Supply Current: 10µA
• Digital Ic Case Style: TSSOP
• Number Of Channels: 2
• Resolution: 16b
• Conversion Rate: 2MSPS
• Interface Type: Serial (3-Wire)
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R/Current Steering
• Power Supply Requirement: Single
• Output Type: Current
• Integral Nonlinearity Error: ±2LSB
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 7. AD5545 Control Logic Truth Table
CS
H
L
L
L
↑+
H
H
H
H
H
1
2
Table 8. AD5555 Control Logic Truth Table
CS
H
L
L
L
↑+
H
H
H
H
H
1
2
POWER-UP SEQUENCE
It is recommended to power-up V
reference voltages. The ideal power-up sequence is A
DGND, V
power-up sequence can elevate reference current, but the device
will resume normal operation once V
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The input leads should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at V
any transient disturbance and to filter any low frequency ripple
SR = shift register, ↑+ = positive logic transition, and X = don’t care.
At power-on, both the input register and the DAC register are loaded with all 0s.
SR = shift register, ↑+ = positive logic transition, and X = don’t care.
At power-on, both the input register and the DAC register are loaded with all 0s.
CLK
X
L
↑+
H
L
X
X
X
X
X
CLK
X
L
↑+
H
L
X
X
X
X
X
DD
, V
LDAC
H
H
H
H
H
L
H
↑+
H
H
H
LDAC
H
H
H
H
H
L
H
↑+
H
REF
x, and digital inputs. A noncompliance
RS
H
H
H
H
H
H
H
H
L
L
RS
H
H
H
H
H
H
H
H
L
L
MSB
X
X
X
X
X
X
X
X
0
H
MSB
X
X
X
X
X
X
X
X
0
H
DD
and ground prior to any
DD
Serial Shift Register Function
No effect
No effect
Shift register data advanced one bit
No effect
No effect
No effect
No effect
No effect
No effect
No effect
Serial Shift Register Function
No effect
No effect
Shift register data advanced one bit
No effect
No effect
No effect
No effect
No effect
No effect
No effect
is powered.
1, 2
1, 2
DD
to minimize
GND
x,
Rev. C | Page 11 of 20
(see Figure 19). Users should not apply switching regulators for
V
frequency.
GROUNDING
The DGND and A
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 19).
DD
due to the power supply rejection ratio degradation over
Input Register Function
Latched
Latched
Latched
Latched
Selected DAC updated
with current SR current
Latched
Latched
Latched
Latched data = 0x0000
Latched data = 0x8000
Figure 19. Power Supply Bypassing and Grounding Connection
Input Register Function
Latched
Latched
Latched
Latched
Selected DAC updated
with current SR current
Latched
Latched
Latched
Latched data = 0x0000
Latched data = 0x2000
V
GND
DD
C2
x pins of the AD5545/AD5555 refer to the
+
10μF
C1
0.1μF
DAC Register
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched data = 0x0000
Latched data = 0x8000
AD5545/
AD5545/AD5555
AD5555
V
A
DAC Register
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched data = 0x0000
Latched data = 0x2000
DD
02918- 0- 008
GND
DGND
X