AD5328BRUZ Analog Devices Inc, AD5328BRUZ Datasheet - Page 17

• Manufacturer Part Number: AD5328BRUZ
• Description: IC DAC 12BIT 2.5V OCTAL 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5328BRUZ

• Data Interface: Serial
• Settling Time: 6µs
• Number Of Bits: 12
• Number Of Converters: 8
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 4.5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 167kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 1mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Control Functions
In the case of a control function, the MSB (Bit 15) is a 1. This is
followed by two control bits, which determine the mode. There
are four different control modes: reference and gain mode, LDAC
mode, power-down mode, and reset mode. The write sequences
for these modes are shown in
Reference and Gain Mode
This mode determines whether the reference for each group of
DACs is buffered, unbuffered, or from V
the gain of the output amplifier. To set up the reference of both
groups, set the control bits to (00), set the GAIN bits, the BUF
bits, and the V
Table 7. Control Words for the AD53x8
D/C
15
1
1
1
1
V
These bits are set when V
first group of DACs (A, B, C, and D) can be set up to use V
setting Bit 0, and the second group of DACs (E, F, G, and H) by
setting Bit 1. The V
When V
has an output range of 0 V to V
GAIN and BUF bits.
BIT 15
(MSB)
BIT 15
(MSB)
BIT 15
(MSB)
D/C
D/C
D/C
DD
A2
A2
A2
Control Bits
14
0
0
1
1
DD
A1
A1
A1
is used as the reference, it is always unbuffered and
Figure 32. AD5308 Input Shift Register Contents
Figure 33. AD5318 Input Shift Register Contents
Figure 34. AD5328 Input Shift Register Contents
A0
A0
A0
DD
Reset
D11
D9
bits.
D7
13
0
1
0
1
DD
D10
D6
D8
bits have priority over the BUF bits.
12
x
x
x
1/0
D9
D5
D7
DD
DATA BITS
is to be used as a reference. The
D8
D6
D4
Table 7
x
x
x
x
11
DATA BITS
REF
D7
D3
D5
regardless of the state of the
DATA BITS
D6
x
.
10
x
x
x
D2
D4
D5
D3
D1
DD
x
9
x
x
x
. It also determines
D4
D2
D0
8
x
x
x
x
D3
D1
0
7
x
x
H
x
D2
D0
0
6
x
x
G
x
D1
0
0
BIT 0
(LSB)
BIT 0
(LSB)
BIT 0
(LSB)
D0
5
E...H
x
F
x
DD
0
0
GAIN Bits
Rev. F | Page 17 of 28
by
4
A...D
x
E
x
Channels
D
x
3
E...H
x
BUF
This controls whether the reference of a group of DACs is
buffered or unbuffered. The reference of the first group of DACs
(A, B, C, and D) is controlled by setting Bit 2, and the second
group of DACs (E, F, G, and H) is controlled by setting Bit 3.
GAIN
The gain of the DACs is controlled by setting Bit 4 for the first
group of DACs (A, B, C, and D) and Bit 5 for the second group
of DACs (E, F, G, and H).
LDAC Mode
LDAC mode controls LDAC , which determines when data is
transferred from the input registers to the DAC registers. There
are three options when updating the DAC registers, as shown in
Table 8
Table 8. LDAC Mode
Bit 15
1
1
1
1
LDAC Low (00): This option sets LDAC permanently low,
allowing the DAC registers to be updated continuously.
LDAC High (01): This option sets LDAC permanently high.
The DAC registers are latched and the input registers can
change without affecting the contents of the DAC registers.
This is the default option for this mode.
LDAC Single Update (10): This option causes a single pulse on
LDAC , updating the DAC registers once.
Reserved (11): reserved.
BUF Bits
0: unbuffered reference.
1: buffered reference.
0: output range of 0 V to V
1: output range of 0 V to 2 V
C
x
2
A...D
x
.
Bit 14
0
0
0
0
B
x
1
E...H
1/0
LDAC Bits
V
DD
Bit 13
1
1
1
1
Bits
1/0
A
x
0
A...D
AD5308/AD5318/AD5328
Bits 12:2
x ... x
x ... x
x ... x
x ... x
Power-down
Mode
Gain of output amplifier and
reference selection
LDAC
Reset
REF
REF
.
.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Description
LDAC low
LDAC high
LDAC single
update
Reserved