AD9754AR Analog Devices Inc, AD9754AR Datasheet - Page 19
![IC DAC 14BIT 125MSPS HP 28-SOIC](/photos/6/59/65912/505-28-soic_sml.jpg)
AD9754AR
Manufacturer Part Number
AD9754AR
Description
IC DAC 14BIT 125MSPS HP 28-SOIC
Manufacturer
Analog Devices Inc
Series
TxDAC®r
Datasheet
1.AD9754ARUZ.pdf
(24 pages)
Specifications of AD9754AR
Rohs Status
RoHS non-compliant
Settling Time
35ns
Number Of Bits
14
Data Interface
Parallel
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
220mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Package
28SOIC W
Resolution
14 Bit
Conversion Rate
125 MSPS
Digital Interface Type
Parallel
Number Of Outputs Per Chip
1
Output Type
Current
Full Scale Error
±5 %FSR
Integral Nonlinearity Error
±3 LSB
Maximum Settling Time
0.035(Typ) us
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9754AR
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9754ARU
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9754ARUZ
Manufacturer:
TI
Quantity:
236
Part Number:
AD9754ARUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9754ARUZ-REEL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Figure 37 shows the AD9754 reconstructing a wideband, or
W-CDMA test vector with a bandwidth of 5 MHz, centered at
15.625 MHz and being sampled at 62.5 MSPS. ACP for the
given test vector is measured at 70 dB.
Figure 37. CDMA Signal, Sampled at 65 MSPS, Adjacent
Channel Power >70 dB
REV. A
–100
–110
–120
–20
–30
–40
–50
–60
–70
–80
–90
13.125
Q DATA
R
2k
I DATA
INPUT
INPUT
FSADJ
SET1
REFIO
CLK
0.1 F
REFIO
REFLO
AD9754
(“Q DAC”)
AD9754
LATCHES
(“I DAC”)
LATCHES
FREQUENCY – MHz
R
1.9k
SET2
FSADJ
DVDD
AVDD
15.625
ACOM
R
220
CAL
DAC
DAC
U2
U1
REFLO
SLEEP
Figure 36. CDMA Transmit Application Using AD9754
AVDD
QOUTA
QOUTB
IOUTB
IOUTA
DCOM
AVDD
100W
100
100
C
FILTER
18.125
500
500
100
500
500
500
CONTROL
500
GAIN
–19–
+3V
500
TXOPP
TXOPN
LOIPP
LOIPN
AD9754 EVALUATION BOARD
General Description
The AD9754-EB is an evaluation board for the AD9754 14-bit
DAC converter. Careful attention to layout and circuit design,
combined with a prototyping area, allows the user to easily and
effectively evaluate the AD9754 in any application where high
resolution, high speed conversion is required.
This board allows the user the flexibility to operate the AD9754
in various configurations. Possible output configurations in-
clude transformer coupled, resistor terminated, inverting/
noninverting and differential amplifier outputs. The digital inputs
are designed to be driven directly from various word generators
with the onboard option to add a resistor network for proper
load termination. Provisions are also made to operate the
AD9754 with either the internal or external reference or to
exercise the power-down feature.
Refer to the application note AN-420 for a thorough description
and operating instructions for the AD9754 evaluation board.
634
500
REFIN
VGAIN
IIPP
IIPN
IIQP
IIQN
CONTROL
FACTOR
2
SCALE
GAIN
COMPENSATION
TEMPERATURE
SPLITTER
PHASE
AD6122
MODOPP
MODOPN
V
CC
AD9754
V
CC